Showing results for 
Search instead for 
Did you mean: 

Vivado CIC broken LV 2018 and 2019


I'm trying to port some code to a Kintex 7 target. One of those code pieces is a CIC filter (Xilinx IPCore).


I can't get the darned thing to work. It will only present me with m_axis_data_tdata ports of 32bit width, irrespective of what is set in the dialog.  Here's an image of a LV2015 node vs 2018 / 2019 node. What on earth am I doing wrong?

ISE 14.7 (Virtex 5 LV 2015)ISE 14.7 (Virtex 5 LV 2015)Vivado 2017.2 (Kintex 7 LV 2019)Vivado 2017.2 (Kintex 7 LV 2019)

Both nodes were configured identically, 4-channel decimating filter (4-fold decimation), frequencies of 40MHz and 160MHz, 20 bit input width, full precision, 28  bit Output width, Latency 19.



0 Kudos
Message 1 of 4

OK, tumbleweeds.


Assuming the CIC compiler is NOT broken, but theinterface has changed (to AXI4), how are the parameters to be defined? Why do the bit widths of the input and output not align with what I have set in the Xilinx IP?


Does anyone have an example of this IPCore from LV 2018 or 2019? Please?

0 Kudos
Message 2 of 4

I have managed to get the thing working.


But there's definitely something fishy about the settings for this IPCore in LabVIEW.  If I configure it for the previous settings, but with 16-bit Input width, hey presto, the input width in the Xilinx dialog and in the LabVIEW dialog match!  If I go to 17 bit, the Input width jumps to 24-bit and the output width jumps to 32-bit.


It seems that the Input and Output widths only change in units of 8 bits.  This is super counter-intuitive for FPGA code and makes working out how to align the data kind of tricky.  For me, with +-20,1 input data but a 24-bit Input width, it works fine if I set the LV dialog datatype to +-24,5 (essentially throwing away 4 bits).  Likewise, the output of width 32-bits is configured as +-32,5.



I have since been able to locate the reason for this on page 43 of THIS document for the IPCore. Apparently, it's an AXI "feature" that everything is handled in blocks of 8 bits.

Message 3 of 4


Can you please explain why you have changed integer word length to (5) instead of word length in LV dialog datatype? If my desired input length of xilinx IP is 20,1 and because of AXI protocol it gives 24,1. how can i compensate it



0 Kudos
Message 4 of 4