Vivado 2015.4 vs. 2014.4 Compile Errors

[Ryan_Smith]

I am using LabVIEW FPGA 2017 with Vivado 2015.4 in Windows 10 and I am getting timing errors. I compiled the same design on LabVIEW FPGA 2015 with Vivado 2014.4 in Windows 10 and I do not get any timing errors and the compile completes successfully.

The design is for a FlexRIO FPGA (PXIe-7971R) with a custom FAM. I have added a constraint file for the design to correct some timing issues a few years ago under Vivado 2014.4. Is it possible that the new version of Vivado uses the constraints differently? The timing violation is definitely in the CLIP for the FPGA.

I am in the process of removing LabVIEW 2017 on the new Windows 10 machine to re-install with LabVIEW 2015 to see if I can replicate the original environment.

Any thoughts?
-Ryan

[Jorr-El]

Hi Ryan,

What sort of timing errors are you seeing? Could you elaborate on the behavior?

Also, if you can, it would be helpful if you could share any screenshots or code to test out. What kind of constraints did you define in your file? Do you have a timing report from your compilation?

Unfortunately, typically the best way to narrow down these kinds of timing issues (particularly if they're not related to logic on the block diagram) is to create a smallest reproducing case. From there, we might be able to determine which VHDL module is responsible for the violation.

Regards,

Jason O

Applications Engineer

National Instruments

[natasftw]

Are you able to give the compile a shot using the cloud compiler?  With Windows 10, I wouldn't ignore the potential for incompatibility.  The cloud would at least eliminate that potential cause.

[Ryan_Smith]

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@natasftw wrote:

Are you able to give the compile a shot using the cloud compiler?

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Unfortunately we are unable to use cloud compile for this design due to policy issues.  We are also moving to Windows 10 due to policy issues, understanding that there may be compatibility issues.

I may try a different design on cloud compile to see what turns up.

[Ryan_Smith]

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@Jorr-El wrote:

What sort of timing errors are you seeing? Could you elaborate on the behavior?

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I need to rebuild my LabVIEW 2017 to get some of this information for you.  I will try to get that done soon to get some data.