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View or process the data acquired by NI 5732

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Hi all, 

 

I have a NI 5732 high-speed digitizer working with NI PXIe 7962R. I need to acquire high frequency data and view/process it online if possible. I think the problem is that the while loop in the top host VI is too slow to read the data sent from the FGPA. I can see the waveform clealy when the input frequency is low, but when the frequency is high the waveform looks ugly. Is there any way I can see the high frequency waveform clealy in real time? Or I can use somethig like a FIFO to store the data and view it later?

 

Thanks,

 

Tong

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Hello Tong,

 

Can you clarify a few things for us?

 

- How high of a frequency is the signal you are trying to acquire? Are we talking kHz or MHz? In order to capture a waveform, you must acquire the signal fast enough to obtain enough samples in a given period to properly represent the signal. NI recommends sampling at 10 times the expected signal frequency to be able to capture both the frequency and shape of that signal.

 

- The loop rate of you FPGA code is what dictates the sampling rate at which you would be acquiring the input signal. Therefore, how exactly do you have your FPGA code set up currently? How are you controlling the loop rates on the FPGA and what loop rate are you configuring?

 

- Can you explain what you mean by: I need to view/process my data “online”? Didyou mean you want to process your data on the FPGA and send only the processed data back to the host VI to view? Please elaborate, thanks!

Matthew R.
Field Applications & Systems Engineer
National Instruments

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I forgot to ask something in my first post:

 

Are you currently using the the NI 5732 - Getting Started exmaple project? 

Matthew R.
Field Applications & Systems Engineer
National Instruments

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Accepted by topic author li1237

Hi Matthew,

 

Thank you for your reply and I already figured out the solution by myself. 

 

I made the FPGA and host VIs by myself according to the "Getting started" example. I'm using the 80MHz internal clock in the FPGA VI. I'm trying to use NI 5732 to acquire signal with frequency of several MHz, so I believe the acquisition rate is fast enough.

 

I solved the problem by using a target-to-host FIFO. The maximum size of this FIFO seemed to be 32767 so I set it to this value. Also in the host VI I set the number of elements read from the FIFO to be 10000. Then I can view the MHz signal in the host VI. 

 

Best,

 

Tong

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Tong,

 

That's great, I am glad you were able to find a solution with your issue! I wish you the best of luck with your applciation. Cheers!  

Matthew R.
Field Applications & Systems Engineer
National Instruments

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