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Using external clock for a SCTL on FPGA (sbRIO9602)

Hi all,

 

i'm working with an ADC and i want to retrieve all data bits (24bits) in synch with serial clock generated by ADC itself...actually i've built a SCTL@40Mhz and implemented also a state machine, looking for rising edge of serial clock and after filling a boolean array with retrieved bit... but this works for a serial clock of 8Mhz...

i must work in the end with a serial clock of 32Mhz so i'm wondering if i can use directly serial clock or better a multiple derived clock to time SCTL to be sure to retrieve all data bits in a robust way..

 

Thanks

 

MR

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As long as you are appropriately able to deal with starts and stops of the external 32 MHz clock, you can certainly use it to run your SCTL. Check out http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgaconcepts/external_clocks/ for more information on using external clocks. You might not be able to oversample quickly enough with that board to capture the I/O using a derived clock from 40 MHz, so using an external clock might be the best place to start if you want the cleanest samples.

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Thanks Dragis, but sorry, i cannot understand how to wire an external clock to a SCTL... 

 

It is better that i clarify what i'm doing:

 

I've built a SPI reading protocol on FPGA:

 

i'm generating a 32Mhz clock as input to ADC in a SCTL clocked@64Mhz...

 

beyond this i have another SCTL@108Mhz to catch bits from ADC when there is a DATA READY pulse ...

 

With actual FPGA VI seems that i can read correctly all 24bits @ 32 Mhz (every data ready pulse happens every 1us so @1Mhz),

 but if i change something in FPGA VI (and soon i have to do this 'cause i have to create an histogram of voltage values delivered from ADC) often happens that at the end of compilation process an error message of timing violation appears... 

i'm wondering if it possible to avoid this due to the fact that ADC delivers a serial clock at same frequency of 32Mhz i think i can take advantage of the fact that bits are in synch with serial clock  @ 32 Mhz and change state on every rising edge.

So my question is how i can use external serial clock delivered from ADC to time SCTL?

 

Thanks in advance.

 

 

 

 

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Mariano,

 

Unfortunately the sbRIO-9602 is not one of our FPGA targets that supports using an external clock source to time SCTLs. However, there is a method that I think you can use that will be effective for application. I've attached a piece of code that clocks in 24 bits of data, one bit at a time on the rising edge of an external clock source (digital input). Once the entire 24 bits has been built into a boolean array, it is put into a target scoped FIFO and sent to a parallel loop for further processing.

 

The reason you are likely seeing timing violations is the combinatorial path of the logic/processing you are adding cannot physically be executed in one tick of the FPGA clock at the speeds you are running your SCTLs. The parallel processing loop in your application could run at any data rate you like so long as you are sure to read elements out of the FIFO at rate equal to write rate.

 

Capture.JPG

Best of luck with the application!

 

Nick C | Software Project Manager - LabVIEW Real-Time | National Instruments
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Thank you very much for your help Nick-C !

 

But i've tried with your implementation but it doesn't work for me... 

seems that filling bits in output array in the same cycle when clock is detected doesn't work...

there must me some delay that comes in play here that at these frequencies must be take in serious consideration i think... 

here i attach the VI i've built based on your example... 

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I post here also the timing diagrams of ADC i hope you can suggest me how to build an FPGA VI to read bits in the best way possible considering that SCLK goes @32 Mhz ... 

i just don't care here about post processing, but i'm interested in take out bits correctly.. maybe there is some rule to create a different clock domain to read bits @32Mhz.... 

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Mariano,

 

Have you tried using or looking at the SPI IP that we have available on FPGA IPNET?

 

Based on your previous posts and the timing diagram that you posted, it looks like the ADC you are interfacing to uses a standard SPI protocol. I would highly recommend starting here rather than trying to build up the entire protocol yourself. I think it'll make for less headaches along the way.

Nick C | Software Project Manager - LabVIEW Real-Time | National Instruments
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