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Using FIFO in communication HOST-FPGA


I'm new to RIO programming.

I need to pass some configuration data from host to FPGA and back, I found a method involving FIFOs. I created a very simple program (picture attached) to learn how it works.

The problem is that the program doesn't work. The variable 'wynik' is 2 regardless inputs 'x' and 'y'.

Hope you can help.


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That code doesn't appear to have any obvious problems. There may be some issue with the configuration of the FIFO, which isn't visible in the pictures.

I also would wonder why you're writing 15 values each time on the RT side, but only reading one result. This will lead to problems with buffer overflow at some point (because you'll be adding 14 elements somewhere each iteration).

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I'm getting the sense that I've already answered this question before.


You need to monitor the "Timeout" output of the FIFO on the FPGA. It will continuously output the last value when the FIFO is empty (it will not automatically return zero).


Only write to the following node if "Timeout" is FALSE.


Aside from that, we have no way of knowing how youe FIFOs are configured. There's a coercion dot on the right-hand FIFO, so there appears to be a datatype mismatch also.

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