Using Block memory FIFO across two clock domains (Labview FPGA)

[avik_airbus]

Greetings!!

   I am developing an applicaiton on the FPGA of the NI 5644R vector signal
transceiver. I have two single cycle timed loops: one 40MHz doing a convolution
and writing to a block memory FIFO, and the second one at 120MHz (sample clock)
which reads from the block memory FIFO and uses the values for subsequent
interpolation...

Under what conditions is it allowed to use a block memory-based FIFO to transfer

values from a 40MHz loop to a 120MHz loop (sample clock)??

The reason I am asking the question is that the compilation of my code repeatedly fails
reporting the below error:

ERROR:HDLCompiler:69 - "/opt/apps/NIFPGA/jobs/J9k7Gwc_WXxzSVD/Interface.vhd" Line 193: <rioclk40outputwstreamwfifocountportfromreshold> is not declared.

For everybody's reference, I am sharing screenshots of my code which is an extension of

the sample "VST streaming project" given in NI5644R. A brief description of the attachments is

given below..

1. "Top_level_FPGA_part1_modification.png": In a 120MHz SCTL loop, a FPGA sub-vi reads

from a block memory FIFO.. Actually, the reading is actually done when the input

"read_stream" is enabled.. (see details in read_from_fifo_true_case.png)

2. "Top_level_FPGA_part2_modification.png": A 40MHz SCTL, in which a FPGA sub-vi is

invoked to write the output of a convolution to the block memory FIFO.

3. "target_respone_fpga_block_FIFO_modification.png": A convolution output from a filter is

written to the block memory FIFO whenever the convolution output is available..

"ReadBlockFIFO" VI (encircled in Top_level_FPGA_part1) is invoked in a 120MHz SCTL.

4. "read_from_fifo_false_case.png": When the "read_stream" input of this vi is false,

transfer of data from block memory FIFO to another FIFO ("Filter to Generation") takes

place.

5. "read_from_fifo_true_case.png": When the "read_stream" is true, data is read from

"Filter to Generation" FIFO and passed on to the subsequent interpolation chain in the

120MHz SCTL...

I hope the attachments give enough clarity of what I am trying to do... If there is a need

for further clarifications, please do not hesitate to ask...

With best regards,

S. Kumar Raja

[avik_airbus · Accepted solution]

Greetings!!

      I think I figured out the problem... The error probably occurs because a DMA FIFO

(host to FPGA) is being read at 40MHz, and it is checked for the number of elements in a loop

at 120MHz.. This is not captured by the "pre-processing" by the labview FPGA, but by the Xilinx

compilation tool during the synthesis stage.

      One lesson I can share is that if you observe this kind of problem, look if there is mismatch

in the clock domains being used to access a FIFO..

With best regards,

S. Kumar Raja