Urgent:How to get analog data from sbRio 9632 ???

[GTHao]

Hi~
I new in Labview~
I want to ask how to get the analog data from SbRio 9632 with FPGA ???
Example
I want to get voltage/current from a solar panel ~ 
So I plug in the device on analog input~
But how to write a program to read the data?
Urgently need help~ thanks~

[kirving]

As far as I know(new to this myself), you'll have to set up an FPGA VI which will take in your analog voltages(using the FPGA I/O node), and write them to variables. These variable can then by read in a seperate VI programmed in Real-Time. This might help: http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpgaconcepts/pfi_data_transfer/

The reason I found this thread though, is that I have a problem with my sbRIO-9626(with RMC card). I've got a sound and vibration module, and a strain input module installed using the RMC, but I can't seem to get any data from either. The sound/vibration module worked initially, and I was able to log acceleration values using the method described above, but when I run the VI now, I get nothing. Anyone have any ideas as to why this might be happening?

[Lennard.C · Accepted solution]

Hi GTHao,

I think you can refer to this manual for sbRIO 9632. It has the step by step guide on how to extract data from sbRIO (though it roughly specifies RIO which includes cRIO but they are more a less the same in terms of getting the analog data for your case)

Please take note of the voltage and current that the sbRIO analog input pins can take before you plug it in.

Hope it helps.

Thank you

Warmest regards,

Lennard C

[GTHao]

Dear Lennard C
May I know~ after I get until the data from analog input~
how to link it to graph??? 
cause I can't link it~ with grey color~

[GerdW]

Hi GTHao,

you need to convert that FXP data to SGL or DBL on the RT side...

[GTHao]

ok~ understand~
so can't do it on FGPA side???
(sorry cause I really new in labview)

[GerdW]

Hi GTHao,

two points:

- SGL support on the FPGA side is a new feature of LV2012, so your request depends on the LV version you use

- it doesn't make sense to use a graph on the FPGA VI, the graph should be on the host side. As the host should be your PC (!) which is the only device with a display in your whole device chain (FPGA<>RT<>PC) you should convert from FXP to SGL/DBL either on the RT or even on the PC...