Underflow issue in LV FPGA Bitfile integration with C Host

[ramyasree]

we are using
LV2018
FPGA Module 2018
RFSA and RFSG 2019
PXIe-5840 FPGA target.

We have implemented OFDMA signal generation code in LV FPGA.we are pushing our final IQ samples to Generation FIFO which is connected
to RFSG modules. This generation should be continuous.Generation FIFO should not empty at any point of time once generation is started.
We have tested that generation with LV host and compiled it.
That bitfile we have integrated with our C code to make it work with C host.
When we are running that code, Generation is fine until when system is not disturbed. When we tried to open another program,
we are facing underflow from Generation FIFO.

when we are tried debugging where it is getting slowed down, we have found FPGA read/write functions in C code are taking longer time than usual at that particular instant. because of that we are observing underflow from the generation FIFO.

Is there any way to solve this issue?

Thanks

Ramyasree

[Intaris]

Without code to look at, it's pointless even starting to try to guess where the problem is

[James_McN]

Hi Ramyasree,

So you are saying that some of the FPGA register read/writes are slowing down and causing the problem? What are the measurements before and after? Can you measure these in LabVIEW and do they show the same change?

What are the other applications doing? Are they talking to the same/similar devices?

A code snippet would really help to understand the structure. Read/Write functions may vary depending on CPU utilisation or bus contention (though this isn't such an issue on PXIe chassis depending on topology). I believe so you may be best not worrying about the difference and instead looking at altering the code structure to make it robust against it (but it depends on what kind of difference we are talking about!)

Just to have all the information the model of your PXI chassis and what the controller/PC is would help identify if there might be hardware issues causing the difference in timing.

[Terry_ALE]

Have you customized the 5840's FPGA? Which FPGA is the FIFO going to?

[Terry_ALE]

Regarding the underflow, what is the data source on the host (disk or software that generates the IQ data)?

What is the IQ rate when you observe the underflow?