Unable to get 3rd DMA to function properly on FPGA R Series Board (PXI-7831R)

[ATE_Dude_22]

I am trying to use a PXI-7831R to generate custom waveforms on 3 AO channels simulatneously. I'm experiencing difficulty getting the 3rd DMA channel to write the correct data. I'm just getting familiar with the LabVIEW FPGA software, so I'm sure there may be something I am trying to do here that is causing the issues I am seeing, but am struggling figuring out how to correct the code to execute correctly.

I've basically modified the example "Analog Output - R Series.lvproj" to allow 3 DMA channels to update the RAM prior to the FPGA executing its code, DMA's 1 & 2 seem to be working, but not DMA 3.

[GregFreeman]

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@ATE_Dude_22 wrote:

I am trying to use a PXI-7831R to generate custom waveforms on 3 AO channels simulatneously. I'm experiencing difficulty getting the 3rd DMA channel to write the correct data. I'm just getting familiar with the LabVIEW FPGA software, so I'm sure there may be something I am trying to do here that is causing the issues I am seeing, but am struggling figuring out how to correct the code to execute correctly.

I've basically modified the example "Analog Output - R Series.lvproj" to allow 3 DMA channels to update the RAM prior to the FPGA executing its code, DMA's 1 & 2 seem to be working, but not DMA 3.

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You don't really say what's wrong, you just say it isn't working. Can you give more detail? Is it possible DMA 3 is overflowing or returning an error? Check the error, and check the "timeout" boolean. You may be getting a timeout, which means you aren't dequeing fast enough on the other end.

[ATE_Dude_22]

Well, the symptoms are that the waveform array being sent to the 3rd DMA was not writing correctly, I was seeing no transitions with the code written as I published when I wrote this post. Since then, I put the FIFO configure and write's for each DMA in its own stacked sequence, and all of a sudden my 3rd DMA started updating correctly (as seen on a O'scope).

At one point, I was monitoring all 3 FIFO's status, and there were no errors going on, but I think I'm going put that monitor back in on all three and see where I am.

The only other prolem I am having right now is the fact that I can't get the FPGA to output anything unless I'm running the host vi in 'debug" mode. Works fine when runing in "debug (i.e. highlight execution)", but as soon as a run full speed, I get nada???

Suggestions?

[GregFreeman]

Would it be possible to post your code? If not, I'll just be speculating.

[ATE_Dude_22]

Here it is.

[GregFreeman]

I am guessing it's not working because your FPGA starts, the tick count times out before you have written your data to your FIFOs. Your FIFOs on the FPGA all have a timeout of 0, so they all timeout then, and your FPGA loop stops (because you have it set to stop on timeout. Now your FPGA is no longer running, so you queue up the data but it never is dequeued and sent by the FPGA. 

Try to set up your FPGA so it does not exit on a timeout and see what happens. I know you have the "run" method on your code after you queue up teh data, but I don't have FPGA installed for LV2012 yet, so I can't open your "open FPGA reference" node. If you open that, is it set to run? This would mean your FPGA is starting right when the reference is opened. Again, I'm just guessing becuase I can't run it. I don't seen anything inherintly wrong though. I'd suggest not stopping your FPGA on timeout, and putting the data writes to the FIFOs in a loop after you ahve started the FPGA. That way it will keep trying to send the data repeatedly and see if you can get it to work. Also, why not put some indicators in your FPGA code you can read on the host, to see if it exits, errors out, etc?

[ATE_Dude_22]

No, its gets set to programatically run AFTER the FIFO's are downloaded. So, the timeout is occuring after the FIFO's have emptied, one of the first things I thought as well.

I'm changing my Onboard Clock to a derived clock of 10MHz, and then setting loop execution speed to 1msec, which should give me 5 seconds of data from a FIFO that's 5000 deep. I thought I was having an "edge" detection issue with my O'scope, so I set the waveform array to go to 5V and stay there for the rest of the FPGA execution, just so I have something to trigger on, and I'm still not triggering??? it's very wierd, because in highlighted execution, everything works just fine.

Thanks for your input.

[GregFreeman]

When highlight execution makes something work, it usually points to timing issues (and by usually I mean about 99% of the time). I'd really suggest putting some indicators in your FPGA code and reading them. Make sure it's truly not starting early. Set a boolean to true once you're in your FPGA loop. Set another boolean to true when your loop exits. Set another to true when your FIFOs timeout/don't timeout. Another when you write to your FPGA IO Node. You get the point. I would suggest putting these "i'm here" indicators all over for the sake of troubleshooting this. I bet something that you are assuming isn't happening, is  actually happening. That always seems to be what gets me in these cases!

[T-REX$]

There are a couple things I would try...

1) monitor the loop count of your FPGA VI... make sure it's not timing out early or anything

2) have you tried simulating this? The first option I would try is Simulation on the Dev computer with File IO ("see the example at /FPGA Fundamentalsl/TestBenches/Custom VI for FPGA IO - Using File IO"). This will show you how to write the expected values to a text file, write the inputs to your AO to a file, and then compare them.