Unable to configure Xilinx IP block

[Graz]

I am running LabView 2014 SP1 with the FPGA module.

When adding a Xilinx RAM-based Shift Register v12.0 to a VI block diagram I cannot configure it.  The help says that there is no license needed.  I get the following output when trying to configure this block (or any other Xilinx IP block that I have tried):

C:\NIFPGA\iptemp\xipinD18DEEF369E44C55AC94D257DA47DD4A>set XILINX_EDK=C:\NIFPGA\programs\Vivado2013_4\ids_lite\ISE 

C:\NIFPGA\iptemp\xipinD18DEEF369E44C55AC94D257DA47DD4A>cmd /c C:\NIFPGA\programs\Vivado2013_4\bin\vivado -mode batch -source "C:\NIFPGA\iptemp\xipinD18DEEF369E44C55AC94D257DA47DD4A\init.tcl" 

****** Vivado v2013.4_(AR59519_AR59812_AR59814_AR60501) (64-bit)
  **** SW Build 353583 on Mon Dec  9 17:49:19 MST 2013
  **** IP Build 208076 on Mon Dec  2 12:38:17 MST 2013
    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: Implementation
WARNING: [Common 17-301] Failed to get a license: Implementation
WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation.

Attempting to get a license: Synthesis
WARNING: [Common 17-301] Failed to get a license: Synthesis
Loading parts and site information from C:/NIFPGA/programs/Vivado2013_4/data/parts/arch.xml
Parsing RTL primitives file [C:/NIFPGA/programs/Vivado2013_4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/NIFPGA/programs/Vivado2013_4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
source {C:\NIFPGA\iptemp\xipinD18DEEF369E44C55AC94D257DA47DD4A\init.tcl}
# set migrated_ip_with_coe false 
# set tempdir {C:\NIFPGA\iptemp\xipinD18DEEF369E44C55AC94D257DA47DD4A}
# set prjdir $tempdir\\temp
# set ipname Shifter_8AB1EDCEB2A048B58E5DA4F7A155DB50
# set ipdir  $prjdir\.srcs\\sources_1\\ip\\$ipname
# set simprjdir  $tempdir
# set simdir $tempdir\\sim
# set simproj $simprjdir\\$ipname\.prj
# set simvhd $simdir\\$ipname\.vhd
# set simvhdports $simdir\\$ipname\_ports\.vhd
# create_project $prjdir -part xc7k70tfbg676-1 -force
# create_ip -vlnv xilinx.com:ip:c_shift_ram:12.0 -module_name Shifter_8AB1EDCEB2A048B58E5DA4F7A155DB50
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/NIFPGA/programs/Vivado2013_4/data/ip'.
# close_project
# open_project $prjdir 
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/NIFPGA/programs/Vivado2013_4/data/ip'.
# set user_ip [lindex [get_ips] 0]
# upgrade_ip $user_ip 
WARNING: [Coretcl 2-1044] upgrade_ip is not supported by 'Shifter_8AB1EDCEB2A048B58E5DA4F7A155DB50'
# if {$migrated_ip_with_coe} {
# set IP_Properties [list_property [lindex [get_ips] 0]]
# foreach IP_Pro $IP_Properties {
# set Val [get_property $IP_Pro [lindex [get_ips] 0]]
# if {[regexp \.coe $Val match]} {
# set_property $IP_Pro $new_coe_file_path [lindex [get_ips] 0]
# break
# }
# }
# }
# set_property IP_OUTPUT_DIR $tempdir [lindex [get_ips] 0]
# set ipvlnv [get_property ipdef [get_ips $user_ip]]
# set ipfile [get_property IP_FILE [lindex [get_ips] 0]]
# set lic [get_property REQUIRES_LICENSE [get_ipdefs $ipvlnv]]
# if {$lic} {
# set fp [open $ipdir\\needlicense.txt w]
# close $fp
# }
WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation.

start_ip_gui: Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 909.457 ; gain = 712.945
# set ip_name [start_ip_gui -ip $user_ip]
# if {$ip_name!=""} {
# 	set_property target_language VHDL [current_project]
# 	set_property simulator_language VHDL [current_project]
# 	generate_target simulation $user_ip
# 	set sim_files [get_files -quiet -all -compile_order sources -used_in simulation -of_objects $user_ip]
# 	file mkdir $simprjdir
# 	set fp [open $simproj "a+"]
# 	if { $sim_files ne "" } {  
# 		foreach file $sim_files {
# 		 set  incomplete_path [string replace $file 0 [expr [string length $tempdir]-1] "<DIR>"]
# 		 set lineinfo "[get_property FILE_TYPE $file] [get_property LIBRARY $file] \"$incomplete_path\""
# 			puts $fp $lineinfo
# 		}
# 		file copy -force $ipfile $tempdir
# 	} else {
# 		generate_target all $user_ip
# 		synth_design -top [find_top] -mode out_of_context
# 		set all_internal_files [get_files -quiet *.vhd -all -of_objects $user_ip]
# 		foreach file $all_internal_files {                                                            
# 			file delete $file                                            
# 		}                                                                                                              
# 		write_vhdl -force -mode funcsim  $simvhd
# 		write_vhdl -force -mode pin_planning $simvhdports
# 		set incomplete_path [string replace $simvhd 0 [expr [string length $tempdir]-1] "<DIR>"]
# 		set lineinfo "VHDL work \"$incomplete_path\""
# 		puts $fp $lineinfo
# 		file copy -force $ipfile $tempdir
# 	}
# 	close $fp
# 	puts "$ip_name is generated successfully."
# }
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'Shifter_8AB1EDCEB2A048B58E5DA4F7A155DB50'...
Generating simulation model for this IP...Vivado Simulator 2013.4
Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
Running: C:/NIFPGA/programs/Vivado2013_4/bin/unwrapped/win32.o/xelab.exe conf_8AB1EDCEB2A048B58E5DA4F7A155DB50 -L work -L unisim -L unimacro -L xilinxcorelib -L secureip -snapshot Shifter_8AB1EDCEB2A048B58E5DA4F7A155DB50 -dll -dll_name xsimk_8AB1EDCEB2A048B58E5DA4F7A155DB50.dll -prj ipinodesim.prj 
Multi-threading is on. Using 6 slave threads.
Determining compilation order of HDL files.
Vivado Simulator 2013.4
Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
Running: C:/NIFPGA/programs/Vivado2013_4/bin/unwrapped/win32.o/xelab.exe conf_8AB1EDCEB2A048B58E5DA4F7A155DB50 -L work -L unisim -L unimacro -L xilinxcorelib -L secureip -snapshot Shifter_8AB1EDCEB2A048B58E5DA4F7A155DB50 -dll -dll_name xsimk_8AB1EDCEB2A048B58E5DA4F7A155DB50.dll -prj ipinodesim.prj 
Multi-threading is on. Using 6 slave threads.
Determining compilation order of HDL files.
ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
Printing stacktrace...

ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
Generated IP unsuccessfully. Fix the above error(s) or warning(s) and generate the IP again.

[vipillai]

Do you have the Xilinx IP Datasheet? 

Are you using the Xilinx IP Node? Which function from the Xilinx IP palette are you using?

If so, what kind of configurations are you doing to this Xilinx IP?

[Graz]

I don't have the Xilinx IP Datasheet.

I don't know what the Xilinx IP Node is.  The Functions pallet has a Xilinx IP with a bunch of blocks in a sub-menu.

The particular block that I am trying to use is the Xilinx RAM-based Shift Register v12.0.

[vipillai]

Could you link me the help page that indicates you do not need licensing for this block?

[Graz]

I am looking at the Context Help for the RAM-based Shift Register 12.0.  I am using LabView 2014 SP1.

[vipillai]

I looked up the error at the end that you're seeing, which is a Xilinx, not LabVIEW error: 

ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received

 I found this forum post indicating it may be related to OS or Xilinx version. 

[Graz]

Do you think that installing the "LabVIEW 2017 FPGA Module Xilinx Compilation Tool for ISE 14.7" and the "LabVIEW 2017 FPGA Module Xilinx Compilation Tool for Vivado 2015.4" from the NI Update Service would help?  I don't have the option of up/downgrading from Windows 7 64-bit and LabView 2014 SP1.

[vipillai]

Which versions of these tools do you currently have? 

[vipillai]

Refer to this chart for compatibility between FPGA module and compilation tools version.

[Graz]

I have 14.7 and 2013.4 installed, which match up with LabView 2014 SP1.  From that table, it looks like I can't just install an upgraded version of the Xilinx tools to fix this.