Unable to compile FPGA with 4 RIO AI modules

[LabVU_Dog]

I have an 8 slot cRIO chassis with 2 9201 modules and 2 9205 modules (and some other digital I/O modules). I developed my FPGA application to get the AI data from all modules and ship it to the RT thru a FIFO with no problem. I added other code to control the digital I/O, including a simple watchdog arrangement with another Compact RIO chassis. All of this would compile and run with no problems. I added the nodes to obtain the scaling/calibration data for the first 9201, and had no problems.

But, after I added the code to get the scaling/calibration data for the 9205 modules, the FPGA SW would not compile anymore. I put all (for all 4 modules) the scaling/calibration code in a subVI. It would compile fine, but if I added it to my main application, the compilation of the main app would fail.

I tried to cut the 9205 nodes down. First I tried only one (9205) module, then only the 10VDC scale/offset. None would compile as part of my whole application. All of them would compile as a stand-alone subVI.

What can I do? Any idea what resource(s) I might be running out of? Is this a normal situation, that I can't get cal and measurement data from a chassis full of AI modules with a single FPGA app?

Thanks in advance.

[Jimmie_A.]

Hello!

You don’t say which controller you are currently using and what kind of messages you get from the compilation report. If you get any error messages post them since they might contain valuable information when troubleshooting. Another thing in the report that is of specific interest is SLICEs since this is the most important measure of your programs size in hardware. The entire process when developing an application is an iterative process and you will notice that the SLICE usage most likely will increase when your application grows in size. There are a few things to consider when trying to fit things on a FPGA such as minimize the number of front-panel arrays, use as small data types as possible and finally try to avoid functions such as “Quotient and Remainder” that consumes lots of space.

[LabVU_Dog]

I have a cRIO 9201 with 9004 controller.

The FPGA compiler indicated that it gets a -1 error and aborts. It did not give me the usual output (successful compilation) of # slices, etc.

I tried a variety of other things to get the code to fit, including consolidating all my boolean inputs and outputs into a single U32 (one control, one indicator). Rather than building an array of all measurements and running that to a FOR loop to put into the FIFO, I accomplished the same without building the array. All were to no avail.

I was finally able to get around the problem by compiling the Calibration VI separately and calling it separately from the RT side as a subVI (the "Call by Reference" equivalent). After the RT has the cal/weighting factors, I download and run the measurement code.

This seems to work fine. But I am amazed that I was not able to find an example of this in any of the cRIO module-specific examples or any of the online resources like the slides from the FPGA training class or any reference to this problem on the message boards.

[Jimmie_A.]

Hello!

Glad you find a workaround, but I am surprised the error message you got wasn’t more helpful. I searched on Xilinx website as well and didn’t found any information about the error for the specific Xilinx FPGA we use.