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Trying to generate a clean square wave on FPGA

I am using a PXI-7842 FPGA module.  I'm trying to output a 10MHz square wave on one of the DIO channels. I am using the Square Wave Generator VI from the FPGA Functions pallet.  I get a somewhat decent square wave up to 1MHz, but at 10MHz, it's a sawtooth wave form.  I am using the FPGA's onboard 40MHz clock. How can I get a cleaner waveform?  Or are there frequency limitations?

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Message 1 of 7

Well, it's either your hardware, your software, or your "measurement-ware" (meaning how you are measuring the square-wave output from the FPGA).  It's hard to comment on your software (we can guess, of course).  Find a good engineer, take her to your setup, and show her the problem, sharing your code with her -- she'll probably find where the problem lies.


Bob Schor

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Message 2 of 7

What cable configuration and length are you using between the hardware.

Could potentially be excess capacitance in the setup causing the square wave to degrade.

But need more details to ascertain the root cause.



"It’s the questions that drive us.”
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Message 3 of 7

Here is the code I'm using.  I've also attached a copy of the VI.  It is a fairly straight forward program.  I'm simply using the supplied function "Generate Square".  I've also attached pictures of the waveforms, using a Tektronix TDS 3034 oscilloscope.



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Message 4 of 7

The cable is the standard NI cable.... 1 meter.

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Message 5 of 7

Have you checked your scope probe?  There should be a place on the scope to hang the probe and have it "see" a "calibration" square wave, where you can adjust the capacitance of the probe to get clean square waves.  Also, is the scope probe ground connected to signal ground?

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Message 6 of 7

Creating the 10 MHz Signal in a FPGA is simple, just toggle a value with 20 MHz 🙂

And now: Wellcome to the analog world 😄

There is a long, never ending 😉 discussion on how much bandwidth you need. ... Infinity in theory ... 20  times the base frequency is a usual pratical value ... .


If you show that signal by hand you will find that as higher the frequncy goes, as more force you need.Newton law (F=ma)


Sort of same for the analog signal. (and even for the 'analog' digital memory cell in the  FPGA ) .. to make it faster you need to make it smaller, reduce the amplitude or you need more energy for switching 🙂


That you see a sawtooth is a strong indicator for limited slewrate (limited force) . If you look closer to your slow signal, I bet you find about the same slewrate there..  So too much load at your signal output (or your scope isn't fast enought.. but this kind of problems vanish nowadays)  . Fast Probes that don't put to much load on a signalsource is still a common problem.

Try an active (expensive) FET- Probe or a correctly compensated 10:1 probe ..

A 10:1 probe has a 9M resistor at the input in parallel with a smaller capacitive load (ten times smalller than your scope input)

Or put more force on the output: Use 4 or 8 outputs in parallel .. but still build a correct termination (here I simplify .. i have no information on the sourceimpedance of one output)




Greetings from Germany

LV since v3.1

“ground” is a convenient fantasy

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Message 7 of 7