Transferring Multiple Channels of Data through DMA FIFO using NI SPI IP

[USF_ENG]

I am reading in 8 channels of SPI data on the FPGA of myRIO using NI SPI IP. I have transferred an array of all 8 channels to the RT Host using the Read/Write Control with clear data loss as I am reading in at 15.625 kHz. I am trying to transfer the array through a DMA FIFO to Host for processing but I'm not sure the best way to get this done. The issue is the NI IP using a SCTL to acquire data and set the SCLK line. The example to Transfer-multiple-channels-of-data-through-one-DMA-FIFO-on-FPGA using an embedded for lop with indexing. I understand how the SCTL can only write one element at a time, so my question is what is the best way to continuously transfer an array of data through the DMA FIFO? The example shows interleaving on the FPGA side then decimate on the Host. Thanks for any help.

[oscarfonseca · Accepted solution]

USF_ENG,

I suggest you try adding an additional step before you send the data back to the RT using a DMA FIFO. Try using an FPGA FIFO to send the single data points to another process (loop) in your FPGA, from where you can interleave the data by channel and send to the DMA FIFO more efficiently.

Let us know your results. Warm regards,

[USF_ENG]

Thanks Oscar that makes sense. I'll give it a try.