I want to transmit data from my host to fpga and then to the Analog output (I am using NI Flexrio and 5782 Adapter module).
I connected a DMA-FIFO( Host to FPGA, I16 DATAtype ) directly to the Analog output Module in a single cycled timed loop running at the IO module clock frequency.
But on compiling the FPGA Vi I am getting the timing violation error.
Please help me to know that why am i getting the error or provide a simple example to do so.
Without your code, we can only guess what is causing the timing violation. I'd guess you're running your clock faster than your DAC can run in the 5782.
The DAC is running at the loop freqencythe error is coming hen i am trying to extract data from the dma FIFO.
I am attaching the VI ....Please help
Why did you use two loops for the transfer? I assume that you used Target-Scoped FIFO to transfer analog input or output values to Target-Scoped DMA loop but it is not necessary. You can write the analog input value to Target-to-Host DMA directly.
By the way, you didn't define a delay so this may be the reason. Please check the examples before going any further. If you still can't use it, let me know.