Transfer FPGA clock value to Host

[cirrusio]

Can you post an image of the FPGA VI?  It could be that the indicator has been optimized out of the compilation. 

[ALST]

Hi all,

The clock edit is done before the run start, so yes I could adapt the host manually to meet this change. However, what I wanted to do is to automatically read this value, in order to avoid changing the Host VI manually every time I use a new clock. It is just a metter of develop a more "flexible" software.

What I think it is just like you suggested, so that the clock value it's like an internal variable of the FPGA., but I can't figure it out why it is so..

Cirrusio, for what concern the VI, I can't really post my real code. However, i attached two simplified version of my program that will show to you the problem.

[GerdW · Accepted solution]

Hi ALST,

The clock edit is done before the run start,

I guess the "clock edit" is done before you compile the FPGA VI?

When you do so you could change a numeric/enum constant and wire it to an indicator in the FPGA code. This way you could create several bitfiles with the same interface to the RT host…

the clock value it's like an internal variable of the FPGA., but I can't figure it out why it is so..

I guess it is so because that clock reference is used to tell the Xilinx compiler which clock signals to generate and use in the FPGA fabric - it's all internal in the FPGA!