I have been using 4 data output, from a constant random differential output source generated.
The 4 data lanes are connected to the RIO 7966 using NI 6587 Adapter module. SERDES channel and SERDES Connector CLIP's are being used, for learning the basics of fpga programming.
I have been referring the following links:
For SERDES ch: http://zone.ni.com/reference/en-XX/help/372614J-01/friohsdio/6587_serdeschan_clipref/ and
For SERDES Cx: http://zone.ni.com/reference/en-XX/help/372614J-01/friohsdio/6587_serdesconn_clipref/
And the fundamentals of fpga programming.
Am learning to communicate with the RIO VI logic's, but I understand after serious study on the above links that.. there is some logic implementation in data transfer - fpga (Wfrm acquisition), while transferring the data from the lane IO to Waveform line's (HOST) shown in the graph which differs with clips talked.
Am unable to get the point as they have some similarity and very small description about both of them!!
I know these are basics, but I greatly appreciate your effort with pleasure if you could lend me some basic idea's on this topics.
Common reference doc: labview-fpga guide for programming
Thanks,
PriyadarsiniS
