Timing violation in labview fpga

[mangood]

Hi member

in figure below you can see an time violation was happen in my IP integration

the problem is how to calculate the maximum frequency from the numbers appeared in red block ???

I try  to connect 150MHZ,140MHZ  time violation also appear !!!!
What is maximum working frequency for this IP block ??

[Dragis]

The timing violation dialog is telling you that your logic needs 10.64 ns to operate. If you invert that, you get a clock route of approximately 90 MHz. So you can change your clock rate to that or you can try rewriting your code to require less time. Since a large portion of your time is in routing logic, you might want to try pipelining your design or rewriting it to require less fanout on signals.

[mangood]

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@Dragis wrote:

The timing violation dialog is telling you that your logic needs 10.64 ns to operate. If you invert that, you get a clock route of approximately 90 MHz. So you can change your clock rate to that or you can try rewriting your code to require less time. Since a large portion of your time is in routing logic, you might want to try pipelining your design or rewriting it to require less fanout on signals.

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Thank you

I try  to use 100MHZ and no timing violation dialog appear..........!! And  timing violation dialog say (inverse of 10.64ns) must use 90MHZ approximately I am confuse now
Is their any wrong???!!!

Use 90MHZ or 100MHZ???
--------------------------------------------------
Finally what is the difference between logic delay and routing delay
as I understand the routing delay is the combinational path delay between two registers 
what about logic delay???
best regards

[Dragis · Accepted solution]

Logic delay is the delay through the actual lookup tables, DSP blocks, etc. The routing delay is the delay between the "real" logic; the delay between the logic blocks including the time to go through the switching matrix. You generally cannot decrease the logic delay without rewriting your algorithm, but you can decrease routing delay by inserting registers to help let the tools move logic around on the chip.

And you have stumbled upon one of the great mysteries of using an FPGA. Sometimes changing the clock rate just a little can cause the tools to generate different code that performs better. In your case, it sounds like the tool could do better and hit 100 MHz. With your original 140+ MHz the tool figured out early on it couldn't hit that rate so it stopped early before doing any further optimizations thus showing you it guessed it could only do around 90 MHz.

[mangood]

okkkkkkkkkkkkkkk

solved with kudes amazing information
ithank for share

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@Dragis wrote:

Logic delay is the delay through the actual lookup tables, DSP blocks, etc. The routing delay is the delay between the "real" logic; the delay between the logic blocks including the time to go through the switching matrix. You generally cannot decrease the logic delay without rewriting your algorithm, but you can decrease routing delay by inserting registers to help let the tools move logic around on the chip.

And you have stumbled upon one of the great mysteries of using an FPGA. Sometimes changing the clock rate just a little can cause the tools to generate different code that performs better. In your case, it sounds like the tool could do better and hit 100 MHz. With your original 140+ MHz the tool figured out early on it couldn't hit that rate so it stopped early before doing any further optimizations thus showing you it guessed it could only do around 90 MHz.

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[FraBaggio1]

Is it possible to ignore timing violations?

[AlexAlligator]

It may be best to go into greater detail in a new thread, but in general we cannot ignore these violations.

If these violations are between a CLIP and the LabVIEW FPGA module block diagram then we can ignore them according to the directions below.

NI KnowledgeBase - How Do I Instruct LabVIEW to Ignore Timing Failures between Component-Level IP (C...

Otherwise we will have to resolve these violations according to the recommendations in the articles linked below.

Troubleshooting Timing Violations (FPGA Module)

Resolving Timing Violations on the FPGA (more detailed but using LabVIEW Comms)

[FraBaggio1]

Thank you Alex. Now I have another problem to solve. This is about testbench simulation and how to measure the output signals with an oscilloscope (see the word attached). I generated a test vector input array that is different for each clock cycle (what is the unit time in the digital input signals graph? is it 25 ns?) and consequently collect the output signals (for that I use a read/write control function for the FPGA target IP integration node) in the host PC. Am I using the third-party simulator? Now how can I see the same digital waveform graph for the output signals with the corresponding delays with respect the input signals (basically I want to repeat the same behavioral test bench seen in VHDL ISIM)? What I see is only the output signals in a waveform chart, whose timing unit is not correlated at all with the input signal. Also how can I see the input and output digital signals in an oscilloscope?

Thank you very much,

Francesco

[SoarOnSon]

Hi Francesco,

To perform debugging in a third-party simulator, you will need to install Questa Simulator or a Xilinx simulator for VHDL code implementation. Please see the link below for more information about what version you will need.

Debugging FPGA VIs Using a Third-Party Simulator (FPGA Module)

Also, please create a new thread to get more visibility for your issue.

Best,

Josh Sorenson
Applications Engineer
National Instruments