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Timed loop iterations end early

I have a timed loop set for a period of 12ms (using the 1kHz system clock).

Looking at the actual start and ends of each iteration, it seems that the loop moves to the next iteration after around 4ms, rather than 12ms.

How can I force the loop iteration to idle until the full period has elapsed?

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Can you show us some simplified code? How do you measure the timing?


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Thanks for your quick response, it's very much appreciated.

Attached is an image of my simplified VI with one of my timed loops. I am coordinating two timed loops hence the synchronised start.

I am using a quad core processor and forcing the other loops and structures onto seperate cores so these shouldn't be an issue.

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In terms of measuring the timing, I take the difference between the actual start and end times, obviously ignoring the first actual end time (and writing this all to a spreadsheet file).

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can you attach the actrual VI instead?

 


@iskrazaf wrote:

I take the difference between the actual start and end times


Shouldn't you take the difference between successive start times?


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The difference between start times is the same as what I am doing, as there is no delay between any of the iterations. I have attached an image of the first few data points from a test run so that you can see for yourself.

Also attached is my VI, but it's quite messy and complex because I'm still in the process of developing the system.

It's for my final year undergraduate thesis project in engineering.

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You are looking at the difference between when the previous iteration ended and when the current iteration began.  You are actually measuring the wait that the Timed Loop put in in order to maintain the loop rate.  If you want to get an actual loop rate, you should look at the Start Times.

 

In your code, I'm seeing a dt of 1.  Why didn't you set that to your 12ms?


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One other thing, why are you setting the dt and mode in every iteration of the while loop, even that it can not change?

 

You have also a lot of sequence structures that are not needed, as the data flow force the correct execution.

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Thanks for your responses guys, really appreciate the help.

 

crossrulz: if you look at my timing data you can see that even if I take the difference in the start times, the loop is still ending early. The column on the left is an array of all the start times for every iteration. This is confirmed by the physical response of the system (a camera and LED setup). Also, the dt in my code is set to a control so that I can play with it when I am testing the system (see LineCapture_v6). I made a very quick simplified VI of my code for altenbach and attached it as a jpeg, so I must've accidentally put a 1 in the dt for that one. But I have definitely had dt set to 12 for my timing data collection.

 

dkfire: I was setting the dt and mode in every iteration as a frustrated attempt to fix it, it was a bit of a last ditch effort that I knew was probably unnecessary. To be honest I'm tearing my hair out here over this, I just can't see why it's not timing properly. The sequence structures are there so that I can force execution onto different CPU cores, I got a new computer so I just was playing around to test the performance.

 

Again I am still very much in the development stage, I haven't cleaned up my code, it's messy, I'm very sorry about that. I swear I'm usually a lot neater 🙂

 

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Sorry, I cannt really investigate your code, because my laptop screen is not big enough. It actually crashes my labVIEW 2014 reproducibly when I press "cleanup diagram". 😞

 

In general, you should take all these timed loops and sequences out of the event structure. What kind of hardware is this running on?


crossrulz wrote:

In your code, I'm seeing a dt of 1.  Why didn't you set that to your 12ms?


You need to look into the other event cases. There are dozens of timed loops and some have a dt determined from a control that is set to 12ms.


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