Timed-loop frequency of 1 MHz

[Cashany]

I've got two codes for my cRIO NI9024; one for FPGA side and one for RT side. 

In my RT code, I'm using a frequency of 1MHz for my timed-loop. 

Just wanted to double check if I should consider some important things when using this frequency or not. 

I mean, is there any special point or hint that I should notice. 

Is there any limitation, any future problem or issue? 

Just for being cautious. 

[ThiCop]

I have some remarks/notes:

- please note that the clock your using is 1 MHz, but the actual frequency/period of your timed loop is 1 kHz (1MHz/dt and dt= 1000)

- Also I don't really see what the waveform indicator is doing in your loop.

  Are you by any chance using local variables to communicate with other parts of your code?

[Cashany]

I avoided uisng local variables because they cause race conditions. 

I'm just using DMA FIFO to transfer data from FPGA to RT. 

This loop transfers 1000 data point from FPGA FIFO to RT in every iteration.

Waveform indicator shows a graph of the time-history of the 1000 accelerations data points transfered from FPGA to RT in every iteration of the loop. 

[ThiCop]

Hello

Is there a specific reason why you need to update it 1000 times per second? (I'm trying to understand teh reason for it)

Is it used for debugging purposes?

If yes, then I would update it alot less often (at least a factor 100) to give your processor a bit more free time.

[Cashany]

Previously, I adjusted the timed-loop nominal frequency to 1 KHz, but the DMA FIFO of FPGA was getting full after a while. 

So, I increased the timed-loop nominal frequency to 1 MHz, and the DMA FIFO of FPGA never got full again. 

Actually I didn't notice to "dt" and the fact that I can play around with "dt" value. 

I think your suggestion is that I can adjust: 

- Nominal frequency of 1 MHz with "dt" value of 100,000 so each loop itreation would execute 10 times each second. Then I can check if the FPGA FIFO gets full or not and if it gets full, I can change the "dt" value to smaller number and check again.  

Or: 

- Nominal frequency of 1 KHz with "dt" value of 100 so each loop iteration would execute 10 times each second. Then I can check if the FPGA FIFO gets full or not ... 

[JÞB · Accepted solution]

I think the point you are missing is that there is never a need to update a graph 1000 times per second!  operators just can't see that fast!  So, unless you are saving that data to disc you can use a much slower update rate.  You may in fact, be throttling that timed loop with your real acquisition rate anyhow (Timeout is 5 seconds-  what is the sample rate of the FIFO?)

If the buffer gets full either reduce the sample rate of the FPGA (really a Million points per second is a lot more than a human eye can process) or increase the number of samples per read.

[Cashany]

Yes, I missed the point that there is no need for updating the graph so fast!

The sampling rate of I/O module of FPGA is around 1652 Sample/sec (that's the minimum supported by NI9234 module).