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Tick Count Express VI outputs '0' on FPGA target running with Simulated I/O

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When I set my target to "Execute VI on Development Computer with Simulated I/O", the Tick Count VIs all output '0 every time they execute. How can I get them to output a progressive count (in the "ticks" instance) or a proper timestamp (in the "ms" instance)?

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Hi David_Staab,

 

What value do you expect from the Tick Count Express VI and can you share a code snippet or the code that shows that the Tick Count Express VI only outputs 0?

 

Also, what version of LabVIEW are you using?

 

Starting with LabVIEW 2013, the Tick Count Express VI uses simulated time rather than real time, when executing your FPGA VI on a development computer with simulated I/O. You can find more information about this in the Version 2013 Features and Changes (FPGA Module) help documentation.

 

Regards,

Tunde S.
Applications Engineer
National Instruments
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I'm using LV 2013 SP1.

 

You want an example VI? Put the "Tick Count" VI in a While loop and connect an indicator to its output. You'll see '0' on every iteration when you run it under simulation.

 

The value I expect is a progressive count (in the "ticks" instance) or progressively incrementing "simulated time" (in the "ms" instance), both with rollover.

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I used LabVIEW 2013 SP1 and I was unable to reproduce this issue on my end. The screenshot below shows my result.

 

tick count.PNG

 

As shown on the Front Panel, the output from the Tick Count Express VI was not 0 on every iteration of the loop.

 

To make sure we are comparing the same code, can you reproduce this issue with the Tick Count shipping example?  You can find this shipping example in the Toolkits and Modules>>FPGA>>CompactRIO>>Fundamentals>>Clocks and Timing>>Tick Count section in the LabVIEW Example Finder.  

 

Regards,

Tunde S.
Applications Engineer
National Instruments
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Oh. Change the While Loop to an SCTL. Sorry.

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I'm unable to reproduce this issue with the Tick Count Express VI in the a Single-Cycle Timed Loop. The screenshot below shows the result, on my end.

 

tick_sctl.PNG

 

Would it be possible for you to share the code that reproduces this issue on your end?

 

Regards,

Tunde S.
Applications Engineer
National Instruments
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Solution
Accepted by topic author David_Staab

Actually it does work as expected. I apologize. When in [ms] mode it ran so slowly that my test VIs looked like they were failing and I didn't notice the value incrmenting when I probed it. I changed the test to use the [ms] instance when running on the FPGA and the [ticks] instance when running with Simulated I/O. This looks like it gives 1 tick every "simulated millisecond" when simulating, and my tests work fine now.

 

Thank you for the help. Sorry again for the false report.

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