The limitation of the FPGA resources when running the FPGA VI

[TCPIP]

  I have writen the FPGA VI and I am using cRIO 9104 FPGA ,  the labview code can be changed to VHDL during the compile, however, in the compilation  report, it shows me that there is the enough resources in the FPGA for me to run the FPGA VI. And the problem I encountered is that I overuse the FPGA resources (SLICE and number of 4 input LUTs).

  In fact, I have put a lot of logic unit such as <, > , =,  different kind of logic gates and the case structure inside the timed loop in the FPGA VI, and I also use certain amount of the memory block and FIFO.

  Which code in the FPGA VI will consume the SLICE resources in cRIO (I suppose it is due to the memory block) and which code in the FPGA VI will consume the number of 4 input LUTs resources in cRIO ( I suppose it is due to the logic unit such as the logic gates and >,<,=...........) ?

  And I have atached 3 of the captured screen pictures to show you the problem.

  Thank you for your help.

[Wiebe@CARYA]

Yes, that happens when you try to put a lot of code in it.

Perhaps if you show some of the code, we can recommend how to make it
smaller.

Regards,

Wiebe.

[DFGray]

Are you using arrays?  They eat resources at a prodigious rate.  Use the memory instead, if you can.  You can also split your VI into two, based on execution time.  Download and execute the first, then the second.  Please post your code and we can be more specific.