Hello,
used hardware: Compact Rio 9035 and NI 9853.
used software: Labview 2017
When i compile the VI "CAN Signals Transmit FPGA.vi", i have this message:
LabVIEW FPGA: The compilation failed due to a Xilinx error.
Details:
ERROR: [Synth 8-1031] cincorrectmodule is not declared [/opt/apps/NIFPGA/jobs2/VWAs7wP_K2iuqv0/Slot_4.vhd:6637]
INFO: [Synth 8-2810] unit behavioral ignored due to previous errors [/opt/apps/NIFPGA/jobs2/VWAs7wP_K2iuqv0/Slot_4.vhd:6555]
INFO: [Synth 8-2810] unit propertycontrolp1slot_4 ignored due to previous errors [/opt/apps/NIFPGA/jobs2/VWAs7wP_K2iuqv0/Slot_4.vhd:7080]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1014.520 ; gain = 177.285 ; free physical = 28246 ; free virtual = 29434
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
9 Infos, 4 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
::RTL Elaboration failed
while executing
"source -notrace ./.Xil/Vivado-2344-ip-10-0-53-140/realtime/toplevel_gen.tcl"
invoked from within
"synth_design -keep_equivalent_registers -top "toplevel_gen" -part "xc7k70tfbg676-1" -flatten_hierarchy "full""
(file "/opt/apps/NIFPGA/jobs2/VWAs7wP_K2iuqv0/synthesize.tcl" line 21)
invoked from within
"source "/opt/apps/NIFPGA/jobs2/VWAs7wP_K2iuqv0/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Thu Jun 14 12:43:31 2018...
Compilation Time
---------------------------
Date submitted: 14/06/2018 14:42
Date results were retrieved: 14/06/2018 14:45
Time waiting in queue: 00:19
Time compiling: 02:49
- Generate Xilinx IP: 00:00
- Synthesize - Vivado: 01:41
Please, can you help me!
Thank you in advance.