The compilation failed due to a Xilinx error.

[kholub]

I recently upgraded from LV2014 to 2015, and a FPGA VI that previously compiled successfully no longer does. My target is a 7951R and I am using a 6584 I/O module. A few minutes into the compilation process, I receive the error below. I have found the NI whitepaper describing this problem for 2010 and providing a patch, but that solution has not been successful for me. Interestingly enough, I can succeed in compiling very simple FPGA VIs, but not more complex ones that were previously viable.

LabVIEW FPGA: The compilation failed due to a Xilinx error.

Details:
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\ODf62Gx_H0cwa34\NiFpgaAG_0000023b_ForLoop.vhd" Line 55: Formal <array_in> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\ODf62Gx_H0cwa34\arrayLpIndx_593.vhd" Line 22. array_in is declared here
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\ODf62Gx_H0cwa34\NiFpgaAG_0000023b_ForLoop.vhd" Line 24: Unit <vhdl_labview> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\ODf62Gx_H0cwa34\NiFpgaAG_0000023b_ForLoop.vhd ignored due to errors
-->

Total memory usage is 239156 kilobytes

Number of errors : 2 ( 0 filtered)
Number of warnings : 11 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Process "Synthesize - XST" failed

Compilation Time
---------------------------
Date submitted: 12/4/2015 4:36 PM
Date results were retrieved: 12/4/2015 4:38 PM
Time waiting in queue: 00:09
Time compiling: 01:44
- Generate Xilinx IP: 00:00
- Estimate Resources - PlanAhead: 00:33
- Synthesize - XST: 00:56

[a_clucker]

Hi kholub,

Can you provide a link the the White Paper you're referencing?

Based on the error, it looks like array_in is not defined. Do you have any loops that you are passing an array to?

Regards,

[kholub]

This is the article I was referencing: http://digital.ni.com/public.nsf/allkb/BBD7A87F2ADC2028862577FB005F6B19

After a bit of experimentation, I believe the 2015 version issue is a red herring. I had moved the VI in question to a new project and when I went back to try and compile it with LV2014, I received the same error. When I went back and tried compiling the original project with 2015, the compilation succeeded. I believe something may have went wrong when I attempted to add my VI to a new project, possibly because I had to recreate my FIFOs and FPGA derived clocks. Is there a better/recommended way of adding a VI which references FIFO/clocks into a new project?

[a_clucker]

Hi kholub,

I'm glad the project compiles.

The best way I've found to change a VI to a new project is:

1. Create and save a new LabVIEW project

2. Add the correct FPGA target

3. Add FIFOs and derived clocks, looking at and copying the settings from the original project while doing so

Note: you can drag FIFOs and derived clocks from one project to another, as long as versioning and models match

4. Copy the VI over into the new project

5. Fix any dependency conflicts that might exist

Kind Regards,

[kholub · Accepted solution]

OK, this was a weird one.

I discovered that there actually was a small change between revisions. I had incorrectly initalized an array by swapping the inputs, so that the array size was 0 instead of N. Normally this would be caught at the beginning of compilation, but that null array was used to initilize a shift register in a while loop, and the output of the while loop fed into a FOR loop, where my FIFOs operate. The while loop/shift register seems to be the critical piece that allowed the compilation to progress as far as it did and present as a Xilinx error. If you remove the while loop then the error is caught early and correctly identified.