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Target to Host DMA FIFO on a NI 9144 Expansion Chassis (EtherCAT)

Here is my current setup:

 

Hardware:

 

cRIO 9025 with 6x32 channel AI modules and 2x16 channel TC modules

NI 9144 with 8x32 channel AI modules connected via EtherCAT to above

 

Software Architecture:

 

FPGA on cRIO 9025 running two FIFOs (Target to Host) pumping AI data and TC data (I cannot use the same FIFO for this because the FXP data returned by the AI/Tc modules have different encoding)

 

Host RT VI is sucking data from the FPGA via FIFO reads and streaming to disk. However, I can't access the 8xAI modules on the NI 9144 with DMA... how am I supposed to read this data?

 

 

 

 

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Message 1 of 11
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It seems I'm forced to use a "Target Scoped" FIFO on the NI 9144's FPGA... what is this? How am I supposed to transfer data from the NI9144 to the cRIO 9025 host VI?

 

I'm trying to do 256 channels at 1000Hz... what other architectures can I use to achieve this? There is basically no documentation describing how to do this.

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Message 2 of 11
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The 9144 chassis doesn't support DMA or fronpanel  control transfer. The only way to get the data to the RT Host is to create User Definded I/O variables in project for each 9144 Slave device. These UDVs support only single values and use the scan engine to transfer the data. Make sure you are not writing tom these UDVs faster then the scan engine transfers the data.

There are examples for this coming with the driver for LV.

 

DirkW

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So basically i should just abandon FPGA completley and do this entire project in Scan Mode?

Message 4 of 11
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That would be the easiest if you like I/O variables. Otherwise you could go hybrid means mix scaned I/O and FPGA with UDVs on 9144 and 9025.

LV 2010 and Ethercat 2.0 introduced progammatic discovery and I/O for 9144.

 

DirkW

 

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I was going to use an expansion chassis with one cRIO 9025 controller but found out that only User IO variables can be used to get data from one to the other.  I decided to go instead with two separate controllers so they each can run their own program and FPGA intelligence and exchange data over CAN.  That way they each have their own smarts and can buffer the exchange of data.  A more expensive solution but then again it is more robust.

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So I just tried reading 32x4 AI modules in Scan Engine mode @ 1000Hz from RT project... terrible. Lags behind by several hundred milliseconds.

 

I would like to see how they expect you to record data on over 128 channels @ 1000Hz.

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Message 7 of 11
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Lags behind what? What are you trying to do? What is your LV version?

The 9144 ethercat scan engine combination is not build for speed, more for deterministic data transfer. 1KHz might be to much for a cRIO but should be easy for a PXI system.

 

DirkW

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What I am trying to do:

 

cRIO 9025 with 6x32 channel AI modules and 2x16 channel TC modules

NI 9144 with 8x32 channel AI modules connected via EtherCAT to above

 

 

Record all channels @ 1000Hz.

 

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Message 9 of 11
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So you are using scan mode to do that? The 9144 needs to switch to active mode and the cRIO doesn't so there could be a 100 ms difference in startup.

Besides that there is no hardware synchronization between RIO I/O and 9144 I/O.However all connected 9144s are harware synchronized to each other.

 

DirkW

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