12-06-2012 12:37 AM - edited 12-06-2012 12:40 AM
I am using a PXI-7841R (Virtex5) and am transferring 32 bit data to the host via DMA FIFO. When reading the FIFO on the host for the first time, the data is "stale" (stale meaning it is not what is currently coming into the FPGA but what came in several seconds ago). I have tried both a Stop and a Configure to clear the FIFOs before I use them. Documentation on both of these say either one will clear the target and host FIFOs. Doesn't help in either case. With the second and subsequent reads, the FIFO then has "valid" data (same data as appearing at the FPGA input node). What is puzzling is that each read does exactly the same thing:
Also interesting: FPGA FIFO is set up for 255 elements. The first 255 elements on the host side contain the "stale" data on the first read. This makes me think the FPGA FIFO never cleared.
Solved! Go to Solution.
12-06-2012 12:45 AM
Oh, and the one other option to clear the FIFO, resetting the FPGA, is not possible as there are other things going on in the FPGA that can't be stopped without hosing up the test configuration.
12-06-2012 11:01 AM
Answered by NI support. The documentation for the FIFO Stop and FIFO Configure is in error. Documentation CARs will be written against these.
These methods only clear the host side FIFO. FPGA FIFO data must be read out until zero elements remain.
07-11-2017 06:19 AM
my Application requires to clear a FIFO in case of an error, so I found this topic.
I took a look at FIFO.Stop (Invoke Method) in LabVIEW 2017 FPGA Module Help and there I read "[...] deletes all data from the host memory and FPGA parts of the FIFO [...]"
Does someone know if this is true today? When did the function change?
Or do the function behave like in 2012 and the help is still wrong?
07-12-2017 07:13 AM
I did some quick tests in LabVIEW 2015 and it seems that FIFO.Stop (Invoke Method) works as written in the help.
I did not receive stale data, neither in host-to-target transfer nor in target-to-host transfer.
03-28-2018 02:57 AM
Using LV/FPGA2016 with a PXI-7813R FPGA module (target to host DMA FIFO), I observed 1,000 samples of stale data following FIFO.stop ... not cleared with the Stop function. I had to Read out data one element at a time until empty to clear the FIFO. Problem solved.
10-10-2019 02:06 AM
I am also facing the same problem in clearing the FIFO. As I read in the forum, I did as follows:
1. FIFO Stop and stop the FIFO Write from FPGA side
2. Wait 25 ms
3. FIFO Read out all the elements
4. FIFO Start
After performing those steps, when I start the FIFO, I get more values. Its not completely read out. I have attached the log file and screenshots of the code.
I would be really helpful, if anyone could help me out.
Have a nice day!
Thanks & Regards,