Target to Host DMA FIFO---actual number of elements

[u436]

Hi,

I have a Target to Host DMA FIFO using block memory. Under the FIFO properties, the "actual number of elements" is stated as 1023 elements.

But when I wire an indicator to the "elements remaining" of the FIFO in the host VI, it says 16384 elements. And I can read that much element from the FIFO.

Why is the actual number of element that much greater?

The data type is U32. And I have a PXIe-7965R FPGA.

Cheers.

[nathand · Accepted solution]

There are two different memory buffers for the FIFO: one on the host, the other on the FPGA.  Data is copied from one to the other.  There can be more space allocated on the host, since there is more memory available there and the host loop probably runs slower than the FPGA.  You can set the host buffer size using an FPGA Invoke Node set to FIFO Configure.

[u436]

Thanks.

[u436]

Hi Nathand,

Thanks for your reply.

A related question...If the host FIFO buffer is larger than the FPGA FIFO buffer, will the data in the host FIFO buffer be sequential if I read the whole buffer at once?

Cheers.

[nathand]

You'll always read the items from the FIFO in the order in which they were inserted.

[u436]

Thanks for the reply Nathand.

What I wanted to ask is: Suppose I have am sampling a continuous signal x1, x2, x3, x4, x5 but say the FPGA FIFO has a buffer depth of only 1. And the host buffer has depth 4.

When I read 4 elements from the host buffer, would the data be in xn, xn+1, xn+2, xn+3. Or should I expect to lose some data points and get something like: xn, xn+3, xn+5, xn+8.

Cheers.

[nathand]

When a DMA transfers occurs, the system copies the FPGA FIFO buffer into the host memory, then empties the FPGA buffer.  No transfer occurs until there is space available.  In your example, you should be able to enqueue 5 elements before you drop data, if you wait long enough between enqueue operations for the DMA transfer to occur.  If you try to enqueue multiple elements very quickly - faster than the DMA transfer can occur - then you'll lose data.  So, either of the situations you describe could occur, depending on the enqueue rate.  I don't know the details of the transfer mechanism and its timing.

[nathand]

Also see the LabVIEW help: How DMA Transfers Work (FPGA Module).

[u436]

OK, thanks again.

I guess the best way to check is to put a sequential input into the FIFO and check if the output is in sequence. It isn't.

Cheers.

[nathand]

By "in sequence" do you mean that you get all the data, or that the data that you do receive is in the correct order?  I wouldn't be surprised if you drop some data, but the data that you do read should be in the order it was written, even if it's incomplete.