04-15-2013 11:44 AM - edited 04-15-2013 11:47 AM
Hi ni
I have vi like below that that have been complied to fpga
the vi have two loop that have execute in parallel in fpga,
I have been worked on xilinx ise 14.1 tools for one year the timing was clear
but when I moved to labview fpga many issues is hidden which are
1-how to calculate maximum frequency for each loop ???
I have capture some image but I did not the right answer
2- number of clock signal or name of clock signal for each loop???
I was supprsed to see three source form xilinx log
3-how to now maximum path that effete on maximum frequency????
best regards
m.s
04-16-2013 10:14 AM
Any help ??!! any information>>!!
I really wait answer..
Dose any one have connection with ni team that have build or have information about labviw view fpga
best regads
04-16-2013 04:36 PM - edited 04-16-2013 04:37 PM
Hi mangood,
I believe that your answers will be included in the Xilinx Log file “XilinxLog.txt”. This includes the Xilinx specific details about the compilation process.
Regards,
04-16-2013 04:50 PM
what about this ???
04-18-2013 11:01 AM
Hi,
The problem come from the frequency of the read/write memory. You have to do both in the same timming domain.
So change you while loop for a timed while loop. But be care full with the SCTL. In FPGA timed while loop execute all the code in one tick of the clock define by the clock input of the timed loop.
regards Marc.
04-18-2013 11:48 AM
@Marc-Henri wrote:
Hi,
The problem come from the frequency of the read/write memory. You have to do both in the same timming domain.
So change you while loop for a timed while loop. But be care full with the SCTL. In FPGA timed while loop execute all the code in one tick of the clock define by the clock input of the timed loop.
regards Marc.
Dear:
""read/write memory. You have to do both in the same timming domain."""
I think their an arbitrate circuit that solve this problem
is this right !!!!
""So change you while loop for a timed while loop.:::
do you mean that ""timed while loop"" is single cycle loop???
-----------------------------------------------------------------------------------------------
the main problem was in value of frequency that appear in the image
specially in this image
80MHZ,313MHZ
these value is vague or unclear
the help of labview say that only the requested frequency less than maximum freq
04-18-2013 02:13 PM
Hi,
Yes, in FPGA Timed while loop is a single cycle loop. As I say in my previous message, all the code in this type of loop will be executed in one cycle. SCTL in LabVIEW FPGA
For the arbitration circuit, I don't know, but in my last FPGA project I have to do the read/write in the same frequency domain.
This image show you the result of the compilation. It appears, you ask 50.00 MHz for the on board clock and the compiler say you can go up to 80.50 MHz. It's the same issu for ChinchClk you can go up to 313.28 MHz.
Regards, Marc.
04-18-2013 03:29 PM
@Marc-Henri wrote:
Hi,
This image show you the result of the compilation. It appears, you ask 50.00 MHz for the on board clock and the compiler say you can go up to 80.50 MHz. It's the same issu for ChinchClk you can go up to 313.28 MHz.
Regards, Marc.
dear Marc:
thank for replay
can please expalin to us this statment ""you ask 50.00 MHz for the on board clock and the compiler say you can go up to 80.50 MHz"""
and what this word mean ""ChinchClk""!!!!!!!
the kit has 50 MHZ frequency,what is realted to above statement
i really did not understand what you mean
its really an ambiguous thing
best regards
m.s
04-19-2013 03:01 AM
Hi mangood,
The default on board clock for the FPGA is 40 MHZ, but you can change this clock. It appears, you have choose to configure the clock at 50 MHz. I think that clock is imposed by the kit. The compiler check which max frequency can be use with you code and that max frequency is 80.5 MHz. It's just an information if you want to change the onboard clock. In other way, if you change something in you code, this value probably change greater or lower.
For "ChinchClk" it's the name of a clock that you use on the FPGA VI.
Regards Marc.
04-19-2013 08:47 AM
@Marc-Henri wrote:
Hi mangood,
The default on board clock for the FPGA is 40 MHZ, but you can change this clock. It appears, you have choose to configure the clock at 50 MHz. I think that clock is imposed by the kit. The compiler check which max frequency can be use with you code and that max frequency is 80.5 MHz. It's just an information if you want to change the onboard clock. In other way, if you change something in you code, this value probably change greater or lower.
For "ChinchClk" it's the name of a clock that you use on the FPGA VI.
Regards Marc.
hi
thank you
now its clear to me
but as i understand from your word that the system request two clock !!!!! one of them its maximum value 80 and other 313??
my broad contain only 50 MHZ clock source!!! and i have only one fpga vi
best rgards