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Synchronizing PXIe 6124 and 5781 IO module sample clock.

I was wondering what the proper way to synchronize a 5781 IO module (mounted on a PXIe-7965R flexrio) and a PXIe-6124 module would be. The clock settings for the 5781 is extremely confusing. I aim to generate a signal at 4MSa/s from the 6124 and read it through the analog inputs at 4MSa/s on the 5781. Right now the phase and amplitude look wrong, presumably because the clocks are out of sync. I know that the 5781's AI are synchronous to 'IO Module Clock 0" which is different from the internal FPGA clock? I am then producing a clock for export on the digital line, but I think I can only make it synchronous to the FPGA clock. But this is producing the incorrect results (phase wraps). What's the proper way of synchronizing these two modules? 

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You need to share the same timebase and start trigger.

1. Timebase

  1. 5784: The FPGA clock on a FlexRIO device is always synchronized to the 10 MHz or 100 MHz clock on the PXI(e) chassis. There is nothing you need to do. Reference: Synchronizing the R Series or FlexRIO FPGA Clocks to the PXI Backplane
  2. 6124: Refer to the shipping example <LabVIEW>\examples\DAQmx\Synchronization\Analog Input - Synchronization.vi

ZYOng_0-1695335543097.png

 

2. Start trigger

  1. 6124: Export the Start Trigger to PXI_Trig using DAQmx Export Signals VI
  2. 5781: Refer to the shipping example <LabVIEW>\examples\R Series\Advanced\RIO Master-Slave to wait for the PXI_Trig

 

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