I am collecting quadrature (x4) encoder information on a PXI-6602 and analog information using a 6052E. I need to synchronize (trigger and sampling) between the two cards.
I think I can use the triggering scheme used here http://zone.ni.com/devzone/cda/tut/p/id/3615, but I'm not sure what the best way is to synchronize the sampling.
Here are the two methods that I believe can be used.
Are they both valid? Is one better than the other?
Route the 20MHz timebase from the 6052E onto the RTSI bus and use it as the reference source for the 6602. The PLL on the 6602 will then phase lock the timebase signals on the 6602 to the 6052E 20MHz. Now the default sample clocks for the 6602 and the 6052E should also be phase locked. Using the onboard sample clocks as the ai sample clock (6052E) and the counter gate (6602) should result in sychronized sampling.
Set the gate for the 6602 counter to the ai sample clock of the 6052E card.
Thanks for any assistance, and best regards,
Thank you for contacting NI support. I was curious as to what your application was. The reason I'm asking is because trying to synchronize a counter and analog input is not a usual case, but I think if I had a better understanding of your overall application I would be able to figure out exactly what it is you need to do.
I need to collect torque and position data starting at the same time (i.e. triggering) and collected at the same sample times (i.e. synchronized sample clock) so that the collected values in each data set are "tied" together in time.
It seems like you have a good idea of how to implement this alreay. Your best bet is to focus on method 1. Since you are using PXI all your signals are routed through the backplane, so you could route the start trigger from the 6052e to the 6602 and this will synchronize your triggering. You can also use the sample clock from the 6052e as the sample clock for the 6602, but keep in mind your sampling will be out of phase slightly due to the signals traveling across the backplane. This will be consistent throughout all of your measurements. The Dev Zone article you attached is a great start and should get you on your way. Let me know if you have anymore questions.
Have a great day,
Thanks for the information. I plan to do the following:
1. use the 6052E 20MHz timebase as the ref clock for the 6602 (i.e. sych the 6602 clock signals to the 6052E 20MHz clock)
2. collect ai on the 6052E using its onboard clock as the ai sample clock and collect encoder data on the 6602 using the 6602 onboard clock as the gate signal.
3. Since the timebases (i.e. clocks) on the boards are synched through the PLL on the 6602, if I sample the ai and encoder data at different sample rates, can I still expect to be able to "line up" the collected data in time?
Thanks for any information!