LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

Synchronizing DAQ in FPGA

Highlighted

As it is possible to sample different FPGA channels (e.g. using some analog input voltage C-series module) at different rates - what are the low level details of synchronization?

 

Using basic FPGA DAQ example code, I would think that this has to be achieved using different loops each with its 'Loop Timer' input different (see attached example). But when writing these to the DMA FIFO to transfer to the RT side of the cRIO platform, to what degree are the samples synchronized? If not how is it possible to synchronize them?

0 Kudos
Message 1 of 7
(163 Views)
Highlighted

In looking at your code, it appears that you are using a single FIFO (Raw_Signals_DMA_FIFO) to send data from FPGA Loop 1 and from FPGA Loop 2 to the RT code running on the cRIO.  This is like having two parallel loops enqueuing data in a single Queue, and having a single "reader" loop dequeing the (arbitrarily-intermixed) data from the two enqueuers.  How do you expect to tell them apart?

 

On the other hand, if you set up two FIFOs, then "synchronization" automatically happens at the FPGA source.  You are starting the two "Producer" loops in synchrony, they are running on independent, parallel "clocks", so the data being placed in the FIFOs should remain in "relative synchrony" (i.e. if one loop runs twice as fast as the other, then every other point of the faster loop will be in synch with a corresponding point in the slower loop, and you can match them up at the Consumer end in the Rio, knowing they were simultaneous in the FPGA).

 

Bob Schor

0 Kudos
Message 2 of 7
(87 Views)
Highlighted

Thanks - yes I knew that using the single DMA FIFO in parallel loops would not be ideal. I imagined that the timestamping would have  to be somehow encoded along with the data if a single were used and then the synchronization done later in the data reduction via SW.

 

I guess my next question was when using two DMA FIFO's - how does one guarantee that they 'start' on the same clock edge. In DAQmx this is done by sharing the same clock, using a trigger and starting the slave before the master. I assume a single master clock is used for all operations on a single FPGA (?) - would one then on the RT side during initialization simply put the FPGA Interface invoke node configured to start the DMA FIFO in a single sequence structure?

0 Kudos
Message 3 of 7
(73 Views)
Highlighted

@aetc wrote:

Thanks - yes I knew that using the single DMA FIFO in parallel loops would not be ideal. I imagined that the timestamping would have  to be somehow encoded along with the data if a single were used and then the synchronization done later in the data reduction via SW.

 

I guess my next question was when using two DMA FIFO's - how does one guarantee that they 'start' on the same clock edge. In DAQmx this is done by sharing the same clock, using a trigger and starting the slave before the master. I assume a single master clock is used for all operations on a single FPGA (?) - would one then on the RT side during initialization simply put the FPGA Interface invoke node configured to start the DMA FIFO in a single sequence structure?


Judging by your VI it appears you are using 16 bit digitizers. You are using the internal clock of the FPGA for timing so you should be synced; you just have to make sure they start at the same time, may I suggest an occurrence? 24 bit DSA's may require a bit more work to synchronize.

 

One suggestion for simplification. Do your different rates share a common multiple? If so, you may be able to simplify to using one loop, one timer and a bit of logic. For example, assume my delay for Digitizer A is 100 ms, the Digitizer B is 150 ms. I make a 50 ms delay clock in a loop. Every 2nd iteration I get digitizer A, every 3rd iteration I get digitizer B, every 6th iteration I get digitizer A and B. Does that make sense? Now all you need is one loop, no worries about starting at the same time etc.

 

mcduff

0 Kudos
Message 4 of 7
(58 Views)
Highlighted

Thanks for both responses!

0 Kudos
Message 5 of 7
(53 Views)
Highlighted

Something like below; you can change the pipelining. (Did not show all cases, but you should have the idea.)

 

snip.pngsnip1.png

snip1.png

0 Kudos
Message 6 of 7
(49 Views)
Highlighted

Thanks!

0 Kudos
Message 7 of 7
(44 Views)