I have two PXIe-1085 chassis, and there are multiple PXIe-4300 boards on the chassis. I want to achieve synchronous acquisition on the two chassis.
I plan to synchronize the boards on the two chassis by Sample Clock Synchronization. Route the sampling clock by using a 6674T on each of the two chassis.
As I only have one chassis now, so I plan to test on one chassis.
Route the sampling clock of the Master PXIe-4300 to 6674T/PFI0,
Connected 6674T/PFI0 and 6674T/PFI1 by wires,
The slave card uses 6674T / PFI1 as the sampling clock.
In addition, the link Synchronization Explained states as below, so I first route the sample clock of the master device to PXIe_DstarC, and then route PXIe_DstarC3 to 6674T/PFI0.
“If the sample clock is routed via the PXI_Trig lines, this delay may be up to ~80 ns. If it is routed via the PXI_DStar lines, the delay may be much lower.”
The final vi is shown below. Send the same signal to the master and slave devices to test the synchronization of the acquisition between the devices, the average delay between the master device and the slave device is 113ns.
I have the following question:
In order to reduce the delay, the sampling clock of the master device is routed to PXIe_DstarC; how is the 6674T/PFI1 routed to the slave device as the sampling clock? The 4300 supports PXIe_DSTAR <A..B> as the sampling clock source, how to choose it, such as PXIe_DSTARA0 as the source.