So I'm running into a similar problem where I'm transferring data from an FPGA target to a host using a DMA FIFO buffer.
I need to transfer four channels worth of 32 bit data to the target and they need to be in sync. Presently I'm stuffing two 32-bit channels into a 64 bit DMA FIFO, and two into another 64 bit FIFO. Unfortunately, however, I have learned that the buffers are being pulled off in the host sometimes 1000-8000 samples out of sync.
I have learned that I can use a custom object FIFO, but it doesn't work for DMA transfers to a host. Is there any other way of getting 128 bits (4x32) from the target to the host, synchronized? Right now my only thought of action is to reduce the 32 bits down to 16 bits and stuff all 4 channels into a 64 bit DMA FIFO buffer, but I need the additional resolution of the 32 bits.
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Since you are having this issue of synchronization between the two DMA FIFO channels, I recommend that you use just one 64-bit wide DMA FIFO channel, and combine two of your 32-bits worth of data into one 64 bit number, and then simply write two 64-bit data elements back to back. You can build an array on the FPGA side, and then pass that into an auto-indexed for loop, in which you enqueue each element into the FIFO. Then you can read the data on your host side, and for every 2 elements you can reconstruct the data. Similarly, you could use a 32-bit wide DMA FIFO channel, and pass the each 32-bit element back to back. The first method might prove to be faster, but I am not positive.
This white paper should shed some light on what I am refereeing to: http://www.ni.com/white-paper/4534/en/
Thanks Matt. I have actually started another thread which I will link to here.
I am familiar with packing channels into the 64 bit buffer. However, this will not work as described in my query above since I have 128 bits of data.