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Synchronization of FIFOs in FlexRIO PXIe-7962R

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I am acquiring digitized data using 16 channels of NI 5751 over PXIe-7962R. I have to do this as fast as possible therefore I am using 4 FIFOs with depth of 32768 elements and width of 64-bit (each symbol takes up 16-bits). 

 

I've recently found out that the FIFOs are not syncronised. Somehow there are arbitrary time-delays between the blocks of data coming from the different FIFOs. The delays stay the same during the acquisation. I am thinking that this is primarily due to the fact that I am not flushing the FIFOs properly during the initiation.

 

Is there any way that I can fix this this such that the FIFOs are syncronized. 

 

I am attaching the  project folder, also the block diagrams for Host.vi and FPGA.vi

 

Any help will be much appreciated!

 

 

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Why do you think individual DMA FIFOs should be synchonized?

Well, if you write into all the FIFOs at the same time at the FPGA (what you do) and if you read the same fixed number of elements at the host (what you also do), then you should get the values as you acquired them, at the same time.

I assume that you get an overlfow or underflow somewhere if your values are not correct. You should check for overflow errors using the timed out at the FIFO Write in the FPGA. The way you check it doesn't work since you need to store the value in e.g. a feedback node. Otherwise any possible timeouts are lost.

Also specifiy a larger buffer at the host side for the FIFO (if nothing is specified its 2 times the buffer of the FPGA side).

And why do you use the Abort method after opening the reference to the FPGA?

 

 

Christian

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Thanks very much for the feedback.

 

- What I have attached is a greatly simplified version of what I am doing. I am actually checking for time-outs the way you have suggested. However, I am only recording the number and the timing of such events. I am not doing anything when they occur. The reason for that is I am not having so many time-outs. During a 10 minute acquisation I get 1 or 2 of them. However, at the beginning of each acquisation, a single time-out of definetely occurs. Do you think that could be the reason for the delay between FIFOs? If so, what should I do in the event that I get time-outs?

 

- How is it possible to specify a larger buffer at the host side? I have specified the depth on the FPGA to be 16384 and then found out that I actually have twice that much. But I have never known that I have the option to specify more than that. 

 

- Honestly I have no idea why I am using the Abort method. I took it as it is from one of the example projects. 

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Hey!

 

Ok, so the order of nodes at the host side should basically be:

 

1. Open FPGA VI Reference without the checkmark in "Run FPGA VI" (rightclick>configure ..)

2. FIFO.Reset (where FIFO is the name of your FIFOs in the project)

3. FIFO.Configure (to manually set the depth of the FIFO at the host side. per default it's 2 times the size of the FPGA size)

4. FIFO.Start (should avoid the first timout you receive)

5. Run VI Method

 

Christian

 

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Accepted by topic author daksoy

Appreciate the feedback!

 

Your earlier post made me realize that it is indeed possible to increase the depth of the FIFOs on the host side (I have 12GB of RAM, ie practically I have no limit). This allowed me to redesign the FPGA such that I am now using a single FIFO instead of four to communicate with the host (running the sampler at 10MHz instead of 50MHz also helped, since I needed 5 clock ticks to serialize the data).

 

So, the problem is solved by utilizing a single FIFO instead of four. Thanks Christian for pointing me to the right directon.

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