Streaming DMA FIFO from FPGA to Host

[pepe70]

Hello!

We are  using cRIO 9014 and NI9222 for acquire analog data. The version of Labview is 2012SP1 with Labview RunTime 8.2.1. Most of application we have seeing in this forum deal with streaming the data from FPGA to RT using DMA FIFO and then transfer back to the host.

We have tried to stream the data from the FPGA to the host directly by saving the file in the host computer. We have done that OK  but we at times the channels get all mixed.

Is it possible to do write into the host computer the file without mixing the data? Below are the FPGA code for streaming the data and the host code. 

Any help will be more than welcome!!

[Catherine-B]

Hi pepe70,

Yes it is possible to interleave data in a DMA FIFO and read it out without getting the channels mixed up. The help article below describes interleaving data and gives some recommendations on how to do this to avoid mixing up channels:
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_fifo_interleave/

One of the important notes in to make the buffer size an integer multiple of the number of channels you are interleaving as this helps to reduce the chance of mixing up data points.

The link below also discusses some best practices when using DMA FIFOs. It may be useful to go through those recommendations to make sure your program is adhering to those recommendations.

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_dma_best_practices/

It is also possible that your buffer is underflowing or overflowing. The article linked above also links to some articles that discuss these errors and ways to check for and handle them. The link below is an example that also shows how to combat channel switching due to overflow:
https://decibel.ni.com/content/docs/DOC-31743