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Split/divide 1D arrary into columns to calculate parity

I bet mine is simpler (and follows the example given in the original post)


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Message 11 of 15
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@crossrulz wrote:

I bet mine is simpler (and follows the example given in the original post)

 


Tim,

It maybe a better solution for desktop but I dont think it will work for FPGA.

I cannot get it to work in 2012 not sure if 2013 is a bit more cleverer in determining the size of the array subset. It should be easy enough to determine the size if the length is a constant but it seems like the compiler is not happy with that situation (at least not in 2012).

Cheers


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Message 12 of 15
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Thanks for the input - Correct the FPGA will not allow for any 2D arrays.  However!

 

I have used combination from all advice and finally come up with a working solution.  the spec changed slightly as the final parity check is on the parity check of the four colums - not the fifth column.  Its hard to see but I have simply skipped out the every 5th ouput from the decimited arrary of 50.

 

Please advise if you think my solution is too heavy on resource and if maybe the loop with X-OR is better.  That said for some reason when I use the loop with X-OR the process repeats and gives me different output every other iteration.

 

please see my solution- i am not saying its the best but its works for now.

 

PARITY_VERSION_001.png

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Message 13 of 15
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The LabVIEW FPGA compiler, although it has come a long way, does not support For Loops with shift registers yet. Therefore, it is still hard to implement generic algorithms with compile-time inferred (deferred) array sizes. If you can choose the size of the array up front, then you can use the index array and compound arithmetic node to do parity checks.

 

Depending on the order of the elements in the node, you can change up the indexing or do some decimation and interleaving to get the format in an order you like (all these rearrangement operations are pretty much free on the FPGA).

 

parity.panel.png

parity.diagram.png

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Message 14 of 15
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I just realized that this post wasn't necessarily talking about an implementation inside a Single-Cycle Loop. If the implementation does not requires the SCL, then a solution with shift registers is perfectly valid. The solution I posted will be properly implemented inside a SCL as well.

 

Sorry if that confused anyone. And I can no longer edit my original post so here you go.

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Message 15 of 15
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