Speed problem on PXIe-6591 DRAM Acess

[old_manXJ]

I have several megabytes in DRAM that are batch loaded.  Once done I need to walk sequentially through the addresses, retrieving the data.  I am working in a 156.25mHz SCTL.  It works fine and I get all the data, but very slowly (relative).  I do a very tight loop of two states.  One does the request and the other does the Retrieve and coverts the data and puts it into a FIFO.  The Retrieve takes hundreds of clocks for each valid data.  There are no other actors associated with the DRAM, I am the only one accessing it.

I found it by putting a counter on the number of clocks with valid/non-valid data.  I am in a very time (aka throughput) application.

[BrandonC1]

Hello,

Are you using architecture similar to the example "Getting Started - External Memory.lvproj". you can find that in the NI Example Finder in LabVIEW at Help>>Find Examples.

The architecture in this would be good to study and potentially emulate to achieve faster DRAM access. 

Brandon

[Intaris]

You need to quque up multiple requests to get anywhere near good throughput.  This is a typical "problem" with DRAM, the first address takes a lot longer than the subsequent addresses when queued.