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Some questions about FIFO implementation

Hi, I'm working on a project to control an industrial manipulator using Labview. At this stage, I'm able to transmit linear and angular velocities from the compactRIO through the LAN to the actual robot, which processes the data and then moves accordingly. The data is transmitted as a char string. I'm looking to implement a FIFO so that the processes of reading user input and sending can run in parallel. What is the difference between adding a new FIFO from target and using the available FIFO vis in the functions palette? Also any tips or mistakes people commonly make when using this approach? Just to be clear, my current solution works well enough, but I need it a bit faster. Also english is not my first language so please excuse any mistake I made. Thanks a lot, any help is really appreciated
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Hey Jcarellanov,

 

There are only a few differences between implementing a FIFO either through the target instantiation in the library and instantiating them explicitly on the block diagram. 

 

Difficulty of Implementation - As you have seen, to implement the FIFO explicitly on the block diagram you have to manage the connection in your code. This will result in a much messier looking block diagram and will force you to code in such a way to allow appropriate access to the stored information. There also comes in some complexity when you try to refer to the FIFOs from different targets.

 

Efficiency - When creating the FIFO via the Project Library, it gives you a simpler implementation but as you are delegating the task of maintaining the FIFO to LabVIEW, it results in the use of more FPGA gates and Look Up Tables (LUTs) than if you were to create the FIFO explicitly. LabVIEW will produce a FIFO structure which is suitable for all scenarios (How the FIFO data will be shared), but if you instantiate the FIFO explicitly you will only make use of the scenarios which apply to your code, therefore you will avoid using up FPGA space unnecessarily. 

 

In terms of any tips I have for using the FIFO, I'd recommend for most projects that the use of the Project Library based implementation should be perfectly fine. It's really helpful to have LabVIEW do a lot of the hard work for you at the expense of some extra gates; although if space is a constraint, it may be better to define it in your block diagram. I'd suggest only using as few FIFOs on your block diagram as you can because it's easy to get lost in a mess of wire; you can try concatenating data and using a For Loop to write all of the data to a FIFO of a particular kind, for shared information, which is great for using one FIFO for data of a particular type.

 

If you're finding that your FIFO is slow, try increasing the number of elements to read and write in your FIFO; but this will still only be limited to the rate at which you're acquiring data. For some modules can try and increasing the data rate through a property node of an I/O node in order to increase the amount of samples acquired. You can use a DCM (Clock multiplier) to drive some operations faster, but you must be wary that you don't incur any timing violations in your code (This is when your code ends up driving the clock source of the FPGA to such a speed that the configured circuitry can't keep up) and you can try to make use of Single Cycled Time Loops (SCTLs) to increase the clocking speed of certain sections of your code phenominally. You can find a good explanation of SCTLs here. There are also great examples in the NI Example Finder (LabVIEW > Help > Find Examples...) for different interesting FPGA configurations.

 

Also your English is great! I hope this helps.

 

Regards,


Alex Thomas, University of Manchester School of EEE LabVIEW Ambassador (CLAD)

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Your English is great : ) I am a little confused about which FIFO implementation you are talking about. You mentioned char strings, are those actually "bytes" flowing through an FPGA FIFO or are you using an RT FIFO somewhere?

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@Dragis wrote:

Your English is great : ) I am a little confused about which FIFO implementation you are talking about. You mentioned char strings, are those actually "bytes" flowing through an FPGA FIFO or are you using an RT FIFO somewhere?


Hey again Dragis,

 

So, when I say target instantiated I mean created by selecting New > FIFO in the Project Library. If you create the FIFO by using the FPGA FIFO nodes then this is what I mean by defining it explicitly on the block diagram.

 

For communication between the Real Time Operating System (RTOS) and FPGA you can try using Direct Memory Access (DMA), which is equivalent to a FIFO between the RTOS and FPGA; you're essentially giving the RTOS direct access to the memory on board the FPGA. DMA is one way only, but you can have more than one of them. To send data from the FPGA to the RTOS, use a Target to Host configured DMA FIFO. You can use it to transport any data type you select in the configuration window; as for their transportation, on their lowest level they are just a stream of bits but LabVIEW can determine which parts make up the individual strings for us.

 

Regards,


Alex Thomas, University of Manchester School of EEE LabVIEW Ambassador (CLAD)

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The FIFO takes instructions form the controls on the front panel and puts a string together to be sent to the remote pc. Right now I´m using a FPGA fifo I guess, what's the diffrence between that and the RT? Thanks for the replies guys.
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Anyway, here's the code if you want to check it out. I could also post the previous implementation (without any optimization whatsoever) if you're interested

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@Jcarellanov wrote:
The FIFO takes instructions form the controls on the front panel and puts a string together to be sent to the remote pc. Right now I´m using a FPGA fifo I guess, what's the diffrence between that and the RT? Thanks for the replies guys.

Hello again Jcarellanov,

 

Real Time (RT) FIFOs are similar to FPGA FIFOs in that they allow deterministic transfer of data in time critical applications; this allows communication of data between non-deterministic and deterministic loops in an RT system. 

 

Here's how it works:

 

RT Systems are used in time critical applications; i.e. certain events must happen over certain periods of time and take a known amount of time to complete; for example, if you wanted to record accelerometer measurements at an exact rate of 1000Hz.

 

Now, in an RT system, you'd have one deterministic (Time critical) loop to take the measurements at precise intervals and you'd have another non-deterministic loop to communicate the data. If you tried to take the measurements and record the data, say, to a text file, in a single loop it may become non deterministic. Therefore, through the use of FIFOs, you can make sure that the measurements are taken at precise intervals then push the data into the FIFO for processing. This prevents any unwanted dependancy between the loops, i.e. to prevent the deterministic loop from waiting for the non deterministic loop to finish saving data before taking another measurement. This reduction of coupling between loops is essential in time critical applications.

 

This sort of implementation could be done with local/global variables, however they are lossy and therefore shouldn't be used in measurement applications. As some different aspects of your program may request access to the same memory resource, this could cause jitter (A variation in desired loop time) in your program. FIFOs, when implemented correctly, will not lose any data; however if they're not read from frequently enough the FIFO may overflow and data could be lost because the oldest element in the queue would be overwritten.

 

FIFOs in FPGAs allow a similar data transfer mechanism; however due to the concurrent nature of FPGAs there isn't an issue of 'priorities'; they're used to ensure there isn't a loss of data. So between the RT System and the FPGA, they have some similarities; but the effects of improper configuration in an RT System has a bigger consequence to RT Systems in terms of jitter.

 

Does this answer your question?

 

Regards, 


Alex Thomas, University of Manchester School of EEE LabVIEW Ambassador (CLAD)

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