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Size of FPGA-any solution?

Waran,

Do or will you have access to LabVIEW FPGA 1.1 (LabVIEW 7.1). This will be required for you to use the SCTL.

Christian L
authored by
Christian L, CLA
Systems Engineering Manager - Automotive and Transportation
NI - Austin, TX


  
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Message 11 of 13
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Here are some suggestions for optimizing your code:

- Remove all general cases that do not apply to your application and protocol. Hardcode the timing parameters for your baud rate and do not use the subVI. Select your parity and stop bit mode and remove the unnecessary cases.

- Rework the overall routine in a SCTL. Currently you have a Case structure with three cases (Load memory, read serila port, write serial port). Inside the second and third case you have sequence structures as you step through the serial protocol. When redesigning your code in the SCTL, use one large case structure to develop a State machine in the SCTL that runs you through all these steps in sequence. Remember that you have to keep the code in each case reason
ably small and you can not use any loops inside the SCTL. To implement a For loop in your new State machine you need to repeat the same step/state N number of times and keep your own counter. Once you have complete N cycles of this step, go onto the next one. Using logic inside your state machine you control the program flow between the different steps.

Christian L
authored by
Christian L, CLA
Systems Engineering Manager - Automotive and Transportation
NI - Austin, TX


  
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Message 12 of 13
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Thanks Chris for a quick response!

I shall try to modify and then I will get back to you.

Waran
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Message 13 of 13
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