Showing results for 
Search instead for 
Did you mean: 

Should I wait in polling loops on FPGA?

Go to solution

When polling on something with a CPU, of course we should add some delay to the loop iteration to prevent maxing out the CPU usage.


On FPGA, I guess this isn't a problem!


My question is, should I use a Wait function in these kinds of loops? (Ok, this is only one case, and not a loop, but it's in a loop!)


Perhaps it costs me some checking (and therefore FPGA space), perhaps it saves some power?


I have no problem in terms of fitting my current code on the FPGA, and no reason to be concerned about power usage, I'm really just curious as to what the best practice is for this kind of loop.

0 Kudos
Message 1 of 2
Accepted by cbutcher

FPGA, therefore no need for the wait.  I would rather have what little resources that timer uses for other things.

There are only two ways to tell somebody thanks: Kudos and Marked Solutions
Unofficial Forum Rules and Guidelines
"Not that we are sufficient in ourselves to claim anything as coming from us, but our sufficiency is from God" - 2 Corinthians 3:5
0 Kudos
Message 2 of 2