Sharing .ctl between FPGA & Real-time targets

[skol45uk]

Hi

A .ctl data type representing a message, has been defined under FPGA, then packaged into a .lvlib and also used by a Real-time target (a cRIO RT). There is RT-FIFO used between the FPGA & RT, and the sharing of the .ctl simplifies transfer of message contents. Elements of the .ctl are arrays.

The problem is, that under FPGA all arrays must be of a fixed size. So the .ctl has fixed size array elements defined. But under RT Fixed size arrays cannot be defined, so whenever I refer to an array element of my .ctl type, I get coercion dots to convert the fixed length arrays to "bounded" arrays.

Why is this? Why can't I perform explicit coercion?

I also understand, that pre LabVIEW 8, you could define fixed size arrays at the RT level, but that it was then taken out. So now, only FPGA supports this type of array. Why was this done? I would have thought fixed size arrays would enable tighter programming and enable avoidance of the memory allocator function, and enable better RT responsiveness?!

Have I found an unintentional loophole to the restriction of fixed size arrays to only FPGA code?

Is the mixing of .ctl modules between FPGA and RT regions acceptable?

Is there a way of expressing explicit conversion from Fixed size array in my .ctl data-type, to a bounded array type as used by the RT, so that I can eliminate the coercion dots?

Thanks for any help you can provide.

[jinfone.t]

Hi skol45uk,

Just to make sure I am understanding the problem correctly, with the DMA FIFO, are you trying to put arrays as FIFO elements into FPGA, and getting the data out in RT? 

What version of LabVIEW are you currently using? 

I don't know whether this would be possible, but could you upload your code for us to take a look at on here?