SOM Vivado integration and IP Core creation

[yuval_yohai]

Hello,

I am looking for a way to generate IP-Core to the SOM sbRIO-9651 module.

Is there a strait forward way to do it or should it be done from Vivado?

Is there a BSP of the SOM for the Vivado environment?

Thanks,

Yuval

[yuval_yohai]

Any reply on this?

[TimothyDug]

Hi Yuval,

I think you are wanting a way to program the FPGA. We have our LabVIEW FPGA Module for that purpose.

If you are wanting to compile your IP, you need a compile tool, and the RIO family of hardware only compiles LabVIEW FPGA code. There may be ways to import HDL/Verilog into LabVIEW FPGA, but you need LabVIEW FPGA regardless.

As for a dev kit, we have the NI sbRIO-9651 System on Module Development Kit. Let me know if that works for you.

The compiler you need for the 9651 sbRIO is Vivado 2015.4 (or you could use the Cloud Compile Service if you have SSP). I think I understood what you were looking for, but please let me know if I can clear anything up.

Thanks!

[yuval_yohai]

Hi,

Just to make clear - I am an avid LabVIEW programmer for the past 20 years, and done more than 50 LabVIEW FPGA projects 🙂

yet ...

I need to do something out of the ordinary this certain project and therefore in need for answers regrading my questions.

Thanks,

Yuval

[natasftw]

Yuval,

Your question isn't entirely clear.  Are you wanting to bring your own IP into the FPGA project? 

You need to do something out of the ordinary.  What exactly is that? 

You've asked about whether or not a Broad Support Package exists.  If I'm understanding this correctly, the purpose of the BSP is to get all of the OS related software in place.  You can perform this functionality by creating an image of the SOM to send to other SOMs (or reset your original SOM to the default software setup).  What are you hoping to do with a BSP?

If your goal is simply to bring external IP into the application, take a look at: http://www.ni.com/tutorial/7444/en/

If this doesn't help, please try to clarify your question.  Listing credentials to someone trying to understand the question you're asking doesn't really help.  No matter how much experience you have, there's always going to be something you don't know.  In those cases, it helps to make sure those trying to help understand exactly what you're trying to do so they can help you find your way to a solution.  Otherwise, you'll get generic answers and find yourself still "in need of answers regarding [your] questions."

To help explain the confusion, take a look at this google search: https://www.google.com/search?q=ip-core+vivado&ie=utf-8&oe=utf-8&client=firefox-b-1-ab

When you see there are zero hits for IP-Core, it should help you to understand the wording you're using isn't universal.  Typically, IP Cores relate to bringing in external code.  Beyond that, who knows what it could mean.

[yuval_yohai]

Hi,

Thanks for your reply, I will try and be more specific.

I need to use the second ethernet port (ETH1) as a GigE vision interface, and have direct access to that port directly from the FPGA.

My application is a special camera interface - i.e. the SOM FPGA is collecting and processing the image and then transfer it through the GigE interface of the SOM. This should be possible by the Zynq FPGA but, unfortunately, is not allowed through the standard LabVIEW setup. ETH1 is only available to the Linux RT and the RT processor of the SOM by creating a suitable CLIP. I don't want to be delayed by any OS but have direct access from the FPGA to ETH1

I need also to be able to import third party IP-Core into my project. I was able to do that using LabVIEW 2013 by using the Coregen application but unable to do it anymore using Vivado.

Another application is attaching USB3 interface to the SOM. For that, again, I need to import the USB3 chip-vendor IP-Core to support it.

Hope I was more clear,

Best regards,

Yuval