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SCTL works with Top-level clock but not slower derived clock

I have some FPGA code where I am reading values from two NI9423 digital sink cards to calculate the frequency of the input.  I originally had each card (8-channels) being read in a SCTL using the top-level clock and everything compiles fine.  I found, however, that measuring frequencies below 50 Hz would give some undesirable and inaccurate measurements.  So I thought that if I slowed the clock down and took less samples/sec that it would have an easier time measuring slower frequencies (my thought process is that perhaps at 40 MHz there is an overflow issue - haven't actually calculated that though).  I made a 20 MHz derived clock and used that for the SCTL but it does not compile.  It gives an error that says the object(s) are not supported in the SCTL - which doesn't make sense because it compiled before when the loop was running faster.

 

Does anyone know why I am running into this problem?  And does anyone know a solution for it - or for being able to measure slower frequencies? Thanks in advance.

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Hello joedowdle,

 

I would agree that using half the clock rate should not cause a timing error for the SCTL as it should now have more time to complete the code within it. Perhaps you can post a VI snippet or a screen shot of this loop so that we may analyze other functions within this loop that may be the cause of a timing conflict. 

Wes W
Application Engineering
National Instruments
www.ni.com/support
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What method are you using to transfer data out of the SCTL (on the assumption that you're doing so)?  Some methods cannot work across clock domains, such as memory blocks (if I remember correctly).  If you're reading a memory block in one clock domain and writing to it in another, you might get an error, although I don't know if it would be the error that you're seeing or something different.

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I'm using a global variable to transfer the data out of the SCTL loop and into a regular while loop - where it is then sent over DMA FIFO to VeriStand.  The hardware I am using is a PXI-7813R with a c-module chassis with a 9423 to measure frequency.  I use the global variable to reduce the number of front panel items to improve performance since I don't need access to any of the controls/indicators directly with using VeriStand.

 

I have attached a screen shot of the portion of code that is causing me the problem. For the time being I came up with a "fix" by putting a case statement inside the loop and add x number of blank cases after the measurement.  As the loop executes it enumerates through one case at a time essentially "slowing" the clock down - really it just forces samples to be taken at a slower rate by reading the measurement case less often. And since it's a SCTL running at 40MHz you can calculate the effective sample rate by dividing by the number of cases.

 

I'd like to just be able to use a derived clock but in a pinch this is working so far.  I got from being able to measure as low as 50 Hz down to being able to measure ~8.4 Hz accurately.

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Hello joedowdle,

 

I have replicated this error and it appears that as is specified in the Error message, the NI-9423 does not support any clock rates that are not a multiple of 40 MHz. In an attempt to circumvent this limitation of the module, I have also tried to change the derived clock, 20 MHz, to be the Top Level clock however this is not supported by the FPGA Target, PXI-7813R, either. The limitation of the FPGA target is further explained in this link, in which it states that supported Top Level Clock rates vary with the FPGA target. Regardless, it appears that due to a limitation of both the 9423 and the FPGA target, the hardware being used will not be able to support a 20 MHz clock rate in a SCTL or as a Top Level clock. Although it appears you have already found a work around for this issue, the other solution may be to simply use a While Loop which would still accommodate the maximum clock rate of the 9423 which is 1 MHz.

 

Wes W
Application Engineering
National Instruments
www.ni.com/support
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Hey! I've got similar situation. I'm using NI 9683 Extender with sbrio. I'm generating pulses of 256 Hz at a clock rate of 20 Mhz but it gives an error... saying that it cannot be executed in Single loop. 

The fpga i/o node is RMC/LVTTL/DIO0

Please guide Thanks

 

 

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@Chishti wrote:

Hey! I've got similar situation. I'm using NI 9683 Extender with sbrio. I'm generating pulses of 256 Hz at a clock rate of 20 Mhz but it gives an error... saying that it cannot be executed in Single loop. 

The fpga i/o node is RMC/LVTTL/DIO0

Please guide Thanks


This is not the same issue as the original message topic. You might want to start a separate thread.

 

Can you share your code and a screenshot of the timing error? I'm using a 9683, and there's no problem putting the RMC/LVTTL IO channels in a SCTL. What other logic is in the same loop? There's probably some other function in the same loop that cannot be used in a SCTL.

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Here I've attached the error as well as the project. Please guide me.

 

 

Thanks 

 

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What have you already tried? Did you read the error message? It would appear that you cannot use that IO node in a single cycle loop with the clock set to 20mhz. Try using the default 40mhz clock.

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Yes, I do read the message. Actually, it's my project requirement to operate on 20MHz. Can you please tell me the possible solution. I'm using sbrio 9607 with 9683 RMC extender.

 

 

Thanks

 

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