SCTL execution problem

[johnsnow34]

Hello everyone,

I'm using SCTL for DDR data acquisition. I know SCTL will execute all logic moduls within one clock cycle. But it's not clear when the execution occurs, e.g. at the rising edge, falling edge or within the whole cycle of the clock?

I putted the dataoutput ports of ADC in SCTL which is drived by external clock - data clock of ADC. Data ports would generate data bits at rising and falling edge of the data clock. Can the data at rising and falling edge both be acquisited within one iteration of SCTL?

[Sam_Sharp]

With regards to it being the rising/falling edge of the clock - why does it matter? The clocks are internal to the FPGA and not exported/available externally.

The SCTL executes all functions within 1 tick of the clock (e.g. 1/40Mhz by default unless using a derived clock).

It sounds like you are trying to capture data which is being transmitted according to an external clock source - this is independent to the speed at which your SCTL timed loop executes (which is driven by clocks internal to the FPGA).

Is that right, or have I misunderstood what you're trying to do?

(Edit: It looks like some FPGA targets support external clocks for SCTLs, is that what you're doing?)

[Intaris]

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@johnsnow34 wrote:

Can the data at rising and falling edge both be acquisited within one iteration of SCTL?

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No*. You'll need a clock running at 2x the speed of your DDR clock. Then you can sample.

*Not with pure LV code. If you move towards VHDL, sure, lots of new options open up.

[johnsnow34]

Hi Sam,

yeah, you are right. That is what I'm doing. Sorry I don't describe it clear. The original post was already edited.

[johnsnow34]

Hi Intaris,

thanks for your reply.

I did it following this post. IDDR on FPGA was used and each dataline is divided to two sperate line for the data at rising edge and falling edge. Then manually modified the code of CLIP. Now I can received the data, but the data seemed to have some problem. I think if SCTL executes logics only at e.g. rising edge, the data on falling edge line still can not be received.

So in this situation, can the data on rising and falling edge lines be acquisited within one iteration of SCTL?

This is the example picture of rising and falling edge lines in SCTL:

[Intaris]

What does "some problem" mean?