Technically, it's not always part of the code.
I created HDL nodes and hooked them up outside of any loop in such a way where feedback is involved. I've ran the VI in this manner and used an oscilloscope to check for a clock delay due to the feedback node. However, the only delay I can account for is a small gate delay nowhere near 20 ns. (I'm using the Spartan 3E Starter Board with an onboard clock of 50 MHz).
Essentially, the feedback node is assumed as a wire in this case. I would like to remove or hide it since it's not really intuitive to a lab full of digital logic students that I would be teaching.