Reliable Bitstream Update for 9066

[DGrayEOS]

I have a cRIO-9066 which I am actively developing on. I am having a lot of difficulting reliably replacing the FPGA bitmap on it. My current method is to run a VI doing the following:

1. Open the VI with an open node configured to use the bitmap file, not the VI, only Dynamic Mode checked on setup dialog
2. Do a Reset to stop the FPGA, if running
3. Do a Download to download the new code
4. Do an Abort to make sure it is NOT running (I run later)

This works sometimes. Other times, I need to do a soft reboot of the 9066 to get it to work. Other times, I need to do a power cycle reboot to get it to work. Even that does not work at other times, then it will mysteriously update after I play around with it awhile. I am sure I am missing something. Any ideas?

Case statement should be where the broken wires are.

[Sam_Sharp]

Are you just trying to run the bitfile when your application runs, or are you trying to have it run headlessly (i.e. run at startup)?

If it's the former, just have your application run/download the bitfile when it starts up:

The open reference will automatically download the bitfile to the target (if it's not the same) and if the box is ticked, run it. No need to reset / download / abort first.

If it's the latter, did you know you can update the bitfile from NI MAX? Select the FPGA target and you have the following options:

Finally, in your FPGA build specification, there's an option here:

[DGrayEOS]

Thanks for info, but what you suggested does not work. That is what I started with. I believe the core of my problem is that if the FPGA is running, it will not update. Thus, I try to make sure it is NOT running when I start, since I am in an R&D enviroment and things change and get aborted in unclean ways a lot. At the moment, I try to remember to hard reboot (power off) the controller before tryinng to run an update. However, when I am working remotely, that is not possible. Thus, the question...