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Reentrancy selection

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Hi all,

For LabVIEW 2015 32bit, i have two same sub VI's(AVG TEMP.vi) running simultaneously for which reentrancy is selected as non-reentrant execution. My understanding of non-reentrant execution is labview allocates single data space in memory for all instances. In this case, both vi's executing simultaneously; will it affect vi's output data? should i make it shared clone or preallocated clone reentrant execution.

 

The AVG TEMP.vi is running on FPGA target

 

Thank you

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A non-reentrant VI will run only one after the other. As you said, the data space is shared.

Depending on how the VI is programmed (i.e. the internal block diagram) that may or may not be a problem.

 

Switching to pre-allocated reentrant will give you one dataspace per call site (i.e. place you drop the VI on other diagrams - 2 in your example image) and they won't have any communication. They will be able to run simultaneously.


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shiva@adi wrote:

The AVG TEMP.vi is running on FPGA target


Can you elaborate on the use of DBL on FPGA? What exactly is running on the RT system and what is running on the FPGA fabric? What does the subVI do?


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Here i have attached internal block diagram, just calculating avg of selected temp channels.

The vi's are running in FPGA, does it have any impact on reentrancy?

 

As you said "A non-reentrant VI will run only one after the other" , will it be executed one after other for each cycle?

 

Thank you

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Accepted by topic author shiva@adi

As altenbach pointed out (or at least hinted at), those aren't running on the FPGA, but on the RT host.

I think the FPGA note was edited in after my response - I don't remember seeing it mentioned.

 

Since you're running on RT in that example, you could using Conditional Tunnels to simplify your code considerably. If you really do want to run on FPGA, you'll need fixed length arrays anyway, so yyou won't Delete from Array, but instead conditionally add to form a sum of the values you want.

None of the indexing with -1 and DFA is necessary.

 

Regarding reentrancy, this VI shown has no issue with using non-reentrant execution in terms of shared data, because the VI doesn't store any state.

 


shiva@adi wrote:

As you said "A non-reentrant VI will run only one after the other" , will it be executed one after other for each cycle?


Yes. Probably. At least, they cannot run at the same time (and so in the same cycle). But you're not on FPGA, so less well defined as to what you mean by cycles (usually the CPU cycles aren't too relevant to LabVIEW programming, unlike on FPGA where you often do care about clock cycles).

 

This still isn't all that optimized, in all likelyhood (you might usually try to avoid the Divide, and perhaps the counting of INPUT could be mitigated elsewhere), but this should at least run on FPGA (note DBL -> SGL datatype change, you can't put DBLs on FPGA (yet - perhaps this might be changed in the future)).

Example_VI.png


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The application is to test vehicle brakes. In FPGA target, the FPGA.vi will only read&write analog IO's and PID control in FXP representation. converting it to DBL format global variable in FPGA_IO_RW_new.vi (using FPGA Read/write control) for calculation purposes and shared to HOST using shared variable. sub vi 'AVG TEMP.vi' is used to calculate average temperatures.

please find attached picture for vi hierarchy.

 

This is my first project in labview, please suggest any better way.

 

thank you

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Hi,

Please look at the project file attachment, need some clarity on which is RT host and FPGA.

Based on my understanding i have marked it on the pic. Correct me if i am wrong.

 

I want to learn in depth about FPGA, it will be helpful if you can share some link.

 

Thank you

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shiva@adi wrote:

Please look at the project file attachment, need some clarity on which is RT host and FPGA.

Based on my understanding i have marked it on the pic. Correct me if i am wrong.


The picture is correct - the items under the "Chassis" section are the FPGA target. "<grey>-FPGA.vi" is a VI on the FPGA, and could be the target of a build specification (for example).

As you can see with the picture you attached, the chassis has a different collection of "Dependencies" to the RT target (which encloses the FPGA target).

 


shiva@adi wrote:

I want to learn in depth about FPGA, it will be helpful if you can share some link.


The online training available with an SSP is pretty good for an introduction to FPGA coding. If you don't have access to the online training (a link is available at the top of the forum, copied here: Online Training (SSP Required) ) then you might have luck reading through some of the KnowledgeBase articles. I'd suggest searching with Google rather than the NI search function (although your mileage may vary!).


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Your AVG... vi is not explicitly part of your project, but dependent on other VIs that are. As a first step, right-click on it and find callers, and see where the caller is running, then drag it into the section.

 

And yes, your subVI code is pure Rube Goldberg. For example your "=TRUE" just returns the input unchanged, so why is it even there?

 

cbutcher gave you one alternative and mentioned some others (conditional tunnel). I doubt you really want to run this on the FPGA. Average temperature readings don't dramatically change within nanoseconds. What is your loop rate?


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