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Received Error -61017 after a compile just completed

I running a PXIe-7961R/NI 6585.  I just complied my fpga vi.  I didn't make any changes to the VI while it was compling and when I went to run the host VI I got Error -61017 occurred at Open FPGA VI Reference POssible reason(s): LabVIEW FPGA: You must recompile the VI for the selected traget.  Are there anyother things that can cause this.  I don't need tjo compile i just did that.  

 

 

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You can point the open fpga reference to either a bitfile or an FPGA VI. If is pointed to an FPGA VI you will get a broken run arrow if the compiler thinks that changes have occured since the last time the VI was compiled. You can avoid the nuances of what constitues a change by just pointing the open fpga reference to a bitfile instead of a VI. 

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@David-A wrote:

You can point the open fpga reference to either a bitfile or an FPGA VI. If is pointed to an FPGA VI you will get a broken run arrow if the compiler thinks that changes have occured since the last time the VI was compiled. You can avoid the nuances of what constitues a change by just pointing the open fpga reference to a bitfile instead of a VI. 


While that workaround is usefull, there are some nice advantages to using the VI or Build interface over the bitfile interface. Are there known bugs in the VI or build interface? This seems to be a fairly common issue.

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No bugs, just behavior that can be a little unituitive at first. For example, moving the project can result in a request for recompile if you let the build spec use the default name for the bitfile. 

 

Using interactive mode for an FPGA VI is helpful, but I don't use it that much these days so pointing to a bitfile is the path of least resistance for me. No right or wrong there, more of a style preference than anything. 

 

 

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Hi!

I just encountered a similar problem, that I am not able to resolve.

System Info: cRIO 9022 and an cRIO-9114 LV2015

Problem: after I have worked half a year without a problem, I suddently receive a error when Open FPGA Vi reference. I have no idea what I have messed up. The FPGA-code was not changed. I ususally use "Open Vi" option in the configuration menu. I also have enabled: "Run the FPGA Vi" and "Dynamic Mode". Mass compilation of the compelte project did not solve the problem. Neither did the recompilation of the FPGA code, or the to delete the config setting on the cRIO.

I constantly get the -61017 error. Interestingly, when I configure OpenFPGARef open BitFile, the RTvi breaks. The error list gives me: "Open FPGA VI Reference Contains unwired or bad terminal " and refers to the OpenFPGAViReference.

 

In emulation mode the FPGA vi works. Checking the signiture of the build file does not give a hint (The bitfile is up to data with the build specification)...

 

Is there any systematic approach to takle this problem? I am compeltely lost!!!

Could it be a hardware problem (FPGA) as well?

 

Best wishes,

Luke

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To solve the problme i was having in the Configure Open FPGA VI Reference I quite using the VI under the Open block.  I swithed to Bitfile and could just select the bit file that was complied and i never saw that problem again.  

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Thanks for the fast reply! The problem is, that the vi containing the OpenFPGARef breaks when I use the bit file even though I did not get any error during compilation. 

The error than refers only to the  OpenFPGARef complaining that wires are missing!

It does not make any sense to me... 

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I also found that if you pass that FPGA Refrence into subVIs and you changed the FPGA interface (I.E. added indicators or controls to the fapga frontpanel) you have to update the refrences in all the sub VIs for the new interface.  

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I know! That gave me allready a hard time to figure out a year ago... But I did not change anthing of the FPGA code. And it also does not explain why LV shows an error when OpenFPGARef is lniked to the binary but no error when it is linked to the vi ...

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Message 9 of 11
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Just an add on. I have solved the problem by directly referring to the bit-file when opening the FPGA-Reference.The first attemp did not work, because I did not provide the cRIO Adr. as input for OpenFPGARef. 

I still have no idea, why I suddenly need the explicit reference to the bit file. Without that, it does not work at all, even though it worked before!!!

In addition, I set up a new FPGA-project, Just flashing the cRIO LED controlled by a RT vi.. This worked without a problem without the explicit reference to the bit file. I used it a couple of times and then (this morning) I have the same problem I had with the Project described above.

I still would be happy to get an idea what has changed / messed up leading to this "problem" described above.

 

Best wishes,

Luke

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