03-09-2022 04:00 AM
How to read encoder pulse NI 9425 and NI 9375. Does this module support a high-speed counter?
03-09-2022 04:33 AM
Hi king,
@kingslykishorej wrote:
How to read encoder pulse NI 9425 and NI 9375. Does this module support a high-speed counter?
Both modules are specified as "7µs": what do you consider as "high-speed counter"?
03-09-2022 04:49 AM
Hi Gerd
With reference to this link,
It has been mentioned that NI 9425 and NI 9375 aren't capable of reading pulses. Can you suggest a way to read pulse from encoder using this hardware in C-RIO 9068?
Note: Currently we have NI 9425 and NI9375 with C_RIO 9068
Thanks in advance,
Kingsly
03-09-2022 05:03 AM
Hi king,
both modules can read their DI signals with 7µs delay or 140kS/s.
As long as your encoder pulses comply with the Nyquist criteria (pulse frequency lower than 70kHz) you can use those modules to read the DI signals. Then you can analyze the signals to count the pulses on your own…
Otherwise you might look for modules allowing use of cDAQ onboard counters or dedicated counter modules.
03-09-2022 05:42 AM
Hi Gerd,
Can please verify whether the given model of encoder is suitable to perform operations with NI 9375 or NI 9425?
https://www.kuebler.com/pdf?5863-5883_FS3_en.pdf
MODEL MAKE: KUBLER
MODEL NO: 8.5863.1224.G223
Thanks in Advance,
Kingsly
03-09-2022 06:07 AM
Hi king,
the linked datasheet refers to FS (functional safety) variants using SSI/BiSS and SinCos signals: you will not be able to read their signals using your simple DIO modules.
On the other hand your encoder type is different to those given in the datasheet…
03-09-2022 06:17 AM
Thanks Gerd,
Can you specify which hardware supports reading SinCos or SSI signals?
Controller and Modules: (C-RIO 9068 with NI 9425 and NI 9375)
With Regards,
Kingsly
03-09-2022 07:14 AM
03-09-2022 07:46 AM
@GerdW wrote:
Hi king,
the linked datasheet refers to FS (functional safety) variants using SSI/BiSS and SinCos signals: you will not be able to read their signals using your simple DIO modules.
That is technically a little bit strongly worded. SSI/BiSS is simply a serial bus, most often only used unidirectionally with the clock being generated by the master and the data being sent from the slave. It can go up to 2Mb/s for SSI and 10Mb/s for BiSS and its signalling level is RS-485 or in other words symmetric 5V logic.
It's perfectly valid to use a slower clock than the maximum 2Mb/s or 10Mb/s so you can implement those protocols with the 140KHz maximum speed of those digital signals.
BUT that requires implementing the SSI/BiSS protocol directly in the FPGA, which is not exactly rocket science but also not a piece of cake. If you have not programmed digital communication logic in FPGA before, it's a major learning experience, that is likely not what the OP would be willing to put up with.