I have two parallel loops running on a RT host on a CRio9022. There are two DMA FIFOs: one of the FIFOs is written to in the top loop, the other FIFO is read from in the bottom loop. I've attached a screenshot of my code.
The problem that I'm having is that I seem to only be able to run one of these loops- for example if I disable the first loop, I can see data coming through for the second loop. Trying to run them in parallel as I believe I have coded it means that only one of the loops runs- it is always the top loop in the code I've attached in the screenshot. Each of the FPGA VIs that are running only use one FIFO, so I believe they should be able to run independently... I was wondering if anyone could shed some light on this?
Solved! Go to Solution.
You can only have a single call to the FPGA in HOST mode, the algorithm that you are displaying, is making two calls to the VI "Open FPGA VI Reference", this is not allowed, which is why the program only works with one of these cycles.
Ing. Jonathan E. Cruz Ortiz
Cel : (+57) 3173669343 - (+57) 3124451894
So I would need to combine the two different FPGA VIs I am currently calling into one?
Thanks for your response