Reading and writing from/to FPGA simultaneously

[MiguelIrusta]

Dear all,

I know that I can write from Host to FPGA with FIFOs, as well as reading from FPGA  back to host and write it in file. It is possible to do it at the same time due to the real parallelism inherent in the FPGA (write from host and read from an external IO channel, for example), but if I want to do it at the same time: -Read a file, pass the data to the FPGA and send it in digital output.

-Read an external input with the FPGA module, pass data to host and write into a file.

It is possible to do that simultaneously without any trouble between processes?It is possible with only one VI in host? Is better to do two VI, one for each case, and use them as subVIs with the FPGA open/close as input-outputs? Would them interfiere between them? Or would be better with two completely different Host VIs? 

Thank you in advance.

Regards,
Miguel.

[GerdW]

Hi Miguel,

yes, read from and write to FPGa can run in parallel!

You can use just one VI or separate VIs.

use them as subVIs with the FPGA open/close as input-outputs?

I don't understand this…

Or would be better with two completely different Host VIs?

You can use separate host VIs for read and write access, they surely would be different…

[MiguelIrusta]

Dear GerdW,

Thank you for your response firstly. What I mean is if in the same Host VI could both programs work at the same time or, even sequentilly, without any disturbance between them (I have not thought yet, but probably two timed loops with some kind of key value). The other option is instead of having both processes in the same VI, do it separatly (each one in a different VI) and then from another HostVI use them as subVIs. Probably it could be less problematic.

Summaraizing:

-Option 1:
     - Host VI in which are the reading and writting blocks.
     - FPGA VI reading and acquiring signals.

-Option 2:

    - HostVI in which data is read and is send to the the FPGA module.

    - HostVI in which data acquired by the FPGA is read and written to a file.

    - HostVI in which the the two HostVI described above are called (Main HostVI).

    - FPGA VI reading and acquiring signals.

Looks simpler the option one, but probably is better the second one aproffiting the fact that I have a dual core processor...what do you think?

Thanks again.

Miguel.

[GerdW · Accepted solution]

Hi Miguel,

it makes no difference between your option 1 and 2 (in terms of CPU usage)!

The only difference is readability of your program when you use subVIs to separate the two tasks "visually"…

all you need are two loops, one for writing data to the FPGA, one for reading from FPGA. Those loops can be in one VI or in two separate VIs…